Acer AL2016 Instrukcja serwisowa - Strona 8

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2.2.3 Scaler IC Mstar CHIP U105 (MST9251A)

- U105 (MST9251A) #160, #161, #166~#171 output 8 bit even LVDS digital data to panel control

circuit through CN105 with a separate differential clock via #164, #165.

- U105 (MST9251A)) #174, #175, ##178~#181,#186,#187 output 8 bit odd LVDS digital data to

panel control circuit through CN105, with a separate differential clock via #176, #177.

- U105 (MST9251A) #201 outputs "DIMMER" PWM signals to control CCFL brightness.

- U105 (MST9251A) #106, #107 output a differential clock to DDR , with a parallel resistor R169

is between MCLK+ and MCLK-.

- U105 (MST9251A) #105,#110, #111, #112, #115, #116, #100, #101, #133, #134, #81, #153 send

series of control signal to DDR.

- Nets AR0~AR11 are address select bus from Scaler to DDR.

-Nets MDATA0~MDATA31 are data bus between Scaler and DDR.

Please refer to MST9251A Pin Assignments table in page

2.2.4 MCU Myson chip U107(MTV312)

- U107 (MTV312) #16 output PANEL_ENABLE high potential to make Q103 conducted, and

then make Q102 conducted, +5V flow to CN105#1, #2, #4 as Panel VDD "VLCD" .

- U107 (MTV312) #9 output CCFL_ENABLE low potential to control Inverter on/off.

- TCLK by Crystal 12MHz input to U107 (MTV312) #11, #12.

2.2.5 DDR Sumsung chip K4D263238G-VC36

-U106 is a frame buffer DDR. Control by Scaler via communication bus.

2.2.6 Regulator Circuit

- +5V is from switching mode power supply for U103 and Panel used.

- +3.3V is from switching mode power supply for U104, U105, U107 used.

- +2.5V generates from +5V through C112 filtering D101 Dropping down and U102 which is

output 2.5V LDO for U105 and U106 used.

- +1.8V generates from +3.3V through C108 filtering by U101 which is output 1.8V LDO, for

U105 used.

3. Inverter circuit

3.1 Low voltage to high voltage circuit

18VDC provides the power for IC501 through F501 from power board; the control signals

Brightness and ON/OFF come from I/F board. ON/OFF signal connect to pin8 of IC501 and makes

IC501 enable. Brightness signal connect to pin7 of IC501 and regulates the panel brightness, R509,

D501, R511, C510 make up a network of delaying time circuit for ON/OFF and R501, R508 make up a

divided voltage network for BRIGHTNESS, C515 is used to dump noise. The operation frequency is

determined by the external Resistor R505 and capacitor C512 connected to pin5 of IC501. BURST

MODE dimming pulse frequency and duty is regulated by I/F board. C513 is used for soft start and

compensation, C514, C508 are used for dump noise.

The output drives, include NDR4, NDRV2, PDRV3, PDRV1 (pins1, 3, 15, 16 respectively) output

square pulses to drive MOSFET U501, U502, U503, U504 and each of U501, U502 U503, U504 is

consist of a N channel MOSFET and a P channel MOSFET. U501 and U502, U503 and U504 work as

full-bridge topology work mode, it is high efficient, zero voltage switching.

During start up, VSEN (pin9 of IC501) senses the voltage at the transformer secondary. When

VSEN reaches 3.0V, the output voltage is regulated. If no current is sensed approximately 1.5 seconds

IC501 shunt off.

The current flowing through CCFL is sensed and regulated through sense resistor R504, R507,

R513, R519, R526 and R530. The feedback voltage through D511, D514, D515, D516, D519, D520,

R514 and C522 connected to Pin11 (ISEN) of IC501, then compared with a reference voltage (1.5V)

via a current amplifier, resulting in PWM drive outputs to full-bridge switches.

Service Manual