ComBlock COM-1826 Podręcznik - Strona 15
Przeglądaj online lub pobierz pdf Podręcznik dla Modem ComBlock COM-1826. ComBlock COM-1826 19 stron. Tdrss spread-spectrum modem
Drukuj stronę2. a frequency profile table can be sent to the
receiver. It consists of a start time followed
by 32-bit frequency offset samples read at 1
second intervals. To prevent sudden
frequency jumps, the table entries are
interpolated linearly.
Once the demodulator has confirmed carrier and
code lock, the above frequency offsets are frozen.
Once locked, the carrier tracking loops tracks the
carrier phase over a very wide frequency range.
Frequency profile table
Users can declare the expected Doppler variation
with time in the form of a frequency profile table.
The Doppler is used to correct the demodulator
expected center frequency. It is also used to correct
the demodulator expected chip rate, after scaling the
frequency by the 3.0777995 Mchips/s / 2.2875 GHz
frequency ratio.
The table is entered in one TCP session whereby
the user (TCP client) opens a TCP connection to
port 1024 and writes the entire frequency table.
The table consists of a 64-bit start time (same
reference as the SDDS time tag, i.e. 250ps units)
followed by up to 4096 32-bit frequency samples.
Each sample represents a nominal center frequency
expressed in units of 125 MHz / 2
steps), sampled at 1s intervals.
The byte order is MSB first.
The frequency table is read (played-back) every
second starting at the specified SDDS start time.
The receiver interpolates linearly 64x between
successive 1s samples so as to minimize
discontinuities. This ensures phase and frequency
continuity. This frequency bias is removed from the
SDDS input samples for the playback duration,
irrespective of the demodulator lock status.
Table playback is mutually exclusive with table
upload. Opening a new TCP session to upload a
new table will immediately stop any playback in
progress.
Because the table is quite small (131Kbits max), the
TCP upload time (2-5ms) is insignificant relative to
the playback duration.
32
(about 29 mHz
A utility is included in the ComBlock Control
Center to upload a binary frequency profile table:
Code Tracking Loop
The code tracking loop is a coherent delay lock
loop (DLL) of the 1
st
order.
Code Acquisition
120 parallel detectors search for code aligment
during the code acquisition phase. During the
subsequent code tracking phase, 3 detectors track
the early/center/late code while the other 117
detectors scan for false lock. The detectors are
staggered ½ chip apart.
Detection is performed in two steps: first a coherent
detector averages the despread signal over ½ a
symbol period. The result is squared and further
averaged over 100 symbols.
The received chip rate must be within +/- 4ppm of
the nominal 3.077799479166 Mchips/s value.
Demodulated data output
Demodulated data is encapsulated within variable-
length UDP frames and send to the specified
destination IP/Port.
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