Bose 3-2-1GS Series II Instrukcja rozwiązywania problemów - Strona 26
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THEORY OF OPERATION
2.2.2.10 DSP
The DSP system comprises of the SHARC microprocessor (21065L, U7000), the FLASH
memory (U7200 [sheet 2, B5]), and the SDRAM (U7300 [B/C3]). The software can essentially
be broken up into two segments: The framework and the DSP functions. The framework
•
•
comprises all of the micro-controller type functions for the 3
2
1 Series II such as the communi-
cations, controlling/monitoring the power amplifiers, and power-up/down. The DSP functions
are the digital audio signal processing functions that exist "inside" the framework, such as the
equalization, array processing, volume control, etc. The following discussion relates only to the
interactive and hardware information about the DSP system.
Booting - On a cold start, the supplies come up with the 3.3V supply being the last to achieve
regulation. This supply is monitored with the reset IC, MAX823 (U6000 [sheet 1, D5]) such that
when a threshold is reached, about 3.1V, the IC brings the DSP system out of RESET. When
this occurs, the DSP boots from the FLASH IC and enters the Standby mode.
Standby - After a cold start or an off signal, the DSP puts the system into a standby mode
where the system draws about 3-4 W off the primary AC. Mainly, the amplifiers are put into
standby mode (low quiescent draw), the CS8415A (U4400 [sheet 1, A7]) and CS4228 (U4000
[C2]) are reset, and the DSP enters the "IDLE16" mode (NOT reset) as this is the lowest power
drain mode for the DSP. In this mode, the TAP input works as described above and the PWM
input looks for any communication via Smart Speaker. On any edge on the COMM line, the
DSP enters its quasi-power-down (quasi-standby) mode and sees if a valid command was
received, if not, then the unit enters the standby mode again. LED action shows what is going
on during this time. Also once a second, the system must "come alive" briefly to toggle the
watchdog timer to prevent a RESET to occur.
Also, on entering standby, the volume parameter is set to the last value, but is bounded in the
range of 20 to 80.
Oscillator - The system clock is derived from the oscillator formed by Y7000 [sheet 1, A6] and
an inverter of U6100. There is an onboard inverter on the SHARC but it was determined to not
have enough gain to reliably start-up the oscillator. R7000 was empirically determined to keep
the power dissipation in the crystal to less than .5mW. C7008, 7009 make up the loading
capacitance to set the correct frequency, 33.333MHz. The SHARC doubles this clock to
66.666MHz which sets the maximums MIPS load of the software.
Reprogramming - Software updating is accomplished via the S/PDIF input. The "file" is a
converted binary image into a stereo PCM format that comprises a header followed by the
image to be flashed (the length of this file is about 2 seconds). This allows the software to be
upgraded from a CD-ROM inserted into the console. When the appropriate Smart Speaker
commands are sent, the DSP reboots into ERC then looks again for an update header before
reading in the actual update image. When the image is read in, the code takes a few seconds
to determine the validity with a checksum. If the checksum fails, then no update occurs. (If
there are still "updates" being presented, then the process will begin again.) If the checksum
passes, the unit then writes the image to the FLASH, a process which takes about 45 seconds
and the LED's blink very rapidly (10 Hz, see above). The update disc/file can then be stopped
during this time safely. When this has completed, the system then reboots into the new code as
if it were a cold start (into standby).
The ERC (Emergency Recovery Code) has been written to a protected area of the FLASH such
that in case a software update crashed or anything else that causes the FLASH to be corrupted,
the ERC will always be available, and therefore rewriting the FLASH is always possible using
the same update procedure.
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