DTK PIM-TB10 Podręcznik użytkownika - Strona 7

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memory, and I/O devices. 00 is the least Significant Bit (lSB)

and 07 is the Most Significant Bit (MSB). These lines are active

.......FIigh ..

ALE, Address Latch Enable:

This line is provided by the 8288 Bus ControllE!r and is used

on the system board to latch valid addresses from the processor.

It is available to the I/O channel as an indicator of a vilid processor

address (when used with AEN).

Processor addresses are latched

~ I I I

with the failing edge of ALE.

I/O CH CK, I/O Channel Check:

This line provides the processor with parity (error) infor

mation on memory or devices in the I/O channel. When this

signal is active low, a parity error would indicated.

I/O CH RDY, I/O Channel Ready:

This line, normally high (ready). can be pulled low (not

ready; by a memory or I/O device to lengthen I/O or memory

cycles. It allows slower devices to attach to the I/O channel with

a minimum of difficulty. Any slow device using this line should

III

drive it low immediately upon detecting a valid address and a

r€'zd or write command.

This lines should never be held low,

longer than 10 clock cycles. Machine cycles (J/O or memory) are

extended by an integral number of ClK cycles.

IRQ2-1R07, Interrupt Request 2 to 7:

These lines are used to signal the processor, that a I/O device

requires attention. They are prioritized with IRQ2 as the highest

priority and

R07 as the lowest. An Interrupt Request are gener

ated by raising an I RO lin~ (low to high) and holding it high, until.

it was acknowledged by the processor (interrupt service routine).

lOR, I/O Read Command:

This command line instructs·an I/O device to drive its data

onto the data bus. It may be driven by the processor or the OMA

controller. This signal is active low.

lOW, I/O Write Command:

This command line instructs an I/O device, to read the data

on the data bus. It may be driven by the processor or the OMA

controller. This signal is active low.

MEMR, Memory Read Command:

This command line instructs the memory to drive its data

into the data bus. It may be driven by the processor or the OMA

controller. This Signal is active low.

MEMW, Memory Write Command:

This command line instructs the memory to store the data

present on the data bus. It may be driven by the processor or the

OMA controller. This signal is active low.

DR01-DR03, DMA Request 1 to 3:

These lines are asynchronous channel requests used by per

ipheral devices to gain OMA service.

They are prioritized with

OR03 being the lowest and OROl being the highest. A request

is generated by bringing a ORO line to an active level (high). -A

ORO line must be held high urltil the corresponding OACK