4DSP AD484 Podręcznik użytkownika - Strona 10

Przeglądaj online lub pobierz pdf Podręcznik użytkownika dla Jednostka sterująca 4DSP AD484. 4DSP AD484 20 stron.

AD484 user manual

3.2 FPGA devices configuration

The FPGA firmware is stored on board in a flash device. The 128Mbit device is partly

used to store the configuration for both FPGAs. In the default CPLD firmware

configuration, the Virtex-4 devices A and B are directly configured from flash if a valid

bitstream is stored in the flash for each FPGA. The flash is pre-programmed in factory

with the default firmware example for both FPGAs.

Figure 3 : Configuration circuit

As shown on Figure 2, a CPLD is present on board to interface between the flash device and

the FPGA devices. It is of type CoolRunner-II. The CPLD is used to program and read the

flash. The data stored in the flash are transferred from the host motherboard via the PCI bus

to the Virtex-4 device A and then to the CPLD that writes the required bit stream to the

storage device. A 31.25 MHz clock connects to the CPLD and is used to generate the

configuration clock sent to the FPGA devices. At power up, if the CPLD detects that an

FPGA configuration bitstream is stored in the flash for both FPGA devices, it will start reading

programming the devices in SelecMap mode.

Do NOT reprogram the CPLD without 4DSP approval

The CPLD configuration is achieved by loading with a Xilinx download cable a bitstream from

a host computer via the JTAG connector. The FPGA devices configuration can also be

performed using the JTAG.

3.2.2.1

DIP Switch

A switch (J1) is located next to the JTAG programming connector (J6) see Figure 4. The

switch positions are defined as follows:

February 2007

AD484 User manual

www.4dsp.com

V1.2

- 10 -