4DSP AD484 Podręcznik użytkownika - Strona 15
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Drukuj stronęAD484 user manual
V1.2
3.5.1 Analog inputs
The module is built around four TI ADS5500 14-bit sampling analog-to-digital. ADCs: Analog
data enters the module via four SMA connectors on the front panel, one for each channel.
Both signals are then conditioned (AC coupling as standard via RF transformers; DC optional
via Texas Instrument amplifier THS4509) before being digitized.
3.5.2 Clock input and reference clock distribution
The ADC devices get their own sampling clock, which can be either on-board generated or
from an external reference or an external clock, common to all ADCs via an SMA connector
on the front panel. All samplings clocks are generated by the same chip. It allows having
them all synchronized to a single reference clock. The on-board clock uses the VCXO locked
on an on-board 10MHz reference. The reference clock also can be external. In that case the
VCXO is still used. It is also possible to input an external clock that is directly used to sample
the analog signals. In all cases, all sampling clocks are synchronized to the same clock
source.
3.5.3 Multi-module Synchronization
Several AD484 cards can be cascaded and still be synchronized since either the external
reference or the external clock can be passed to the next module in the chain. The external
reference goes through a 0-delay buffer and is then output via an SMA connector on the front
panel. Please note that synchronisation is in frequency and not in phase.
AD484 User manual
February 2007
www.4dsp.com
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