Fujitsu PRIMEPOWER 850 Biała księga techniczna - Strona 12
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PRIMEPOWER 650 and 850 Technical White Paper
As shown in the figure below, the data system is divided into four groups. Each group connects with four CPUs and an
I/O bridge.
Memory is also divided into four parts, with each part controlled by a SC and addresses are interleaved between two SCs
on the system board. For applications that frequently access contiguous addresses, the memory is interleaved between the
four SCs extending over the system boards. Performance is further improved by interleaving the memory between the
four memory modules. In SDRAM, a group of bytes is set to select status for an address specified as the low address. If
the low address, at the next memory access, matches, continuous memory access is enabled as the select status is already
set. This technique is called low address matching.
The data in memory is protected using ECC, where single-bit errors are corrected automatically. ECC is also employed
in the DTAG, used to maintain cache coherency. In addition, cache, memory, and TAG of the processor are all protected
using ECC. The memory module of this model uses a configuration that enables memory to be continuously used even
if one of the memory elements of the memory module fails completely. This method, previously adopted in high-end
PRIMEPOWER 800 1000 and 2000 systems, is now applied to these 8-way class models. As a result high data path
reliability is also achieved in these new models.
01/12/31
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