Chrontel CH7219 Nota aplikacyjna - Strona 9
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TX0
TX0B
GND
TXC
TXCB
• HPD_HM
This output pin connects to the GND through a 47KΩ resistor. Refer to Figure 10 for the design example.
2.8
Thermal Exposed Pad Package
The CH7219 is available in a 68-pin QFN package with exposed thermal pad. The advantage of the exposed thermal
pad package is that the heat can be dissipated through the ground layer of the PCB more efficiently. When properly
implemented, the exposed thermal pad package provides a means of reducing the thermal resistance of the CH7219.
Careful attention to the design of the PCB layout is required for good thermal performance. For maximum heat
dissipation, the exposed thermal pad of the package should be soldered to the PCB as shown in Figure 11.
Exposed Pad
Solder
PCB
206-1000-058
Rev. 0.1
U1
TX2
1
TMDA Data2+
3
TX2B
TMDA Data2-
GND
5
GND2
7
TX0
TMDA Data0+
TX0B
9
TMDA Data0-
11
GND
GND4
13
CEC
15
DDC_SCL
SCL
GND
17
DDC/CEC Ground
19
HPD_HM
HPDET
R1
47K
HDMI TX (TY PE A)
U2
U3
1
10
1
TX0
TX2
I/O 1
I/O 8
I/O 1
2
9
2
TX0B
TX2B
I/O 2
I/O 7
I/O 2
3
8
3
GND
GND
GND
GND
GND
4
7
4
TXC
TX1
I/O 3
I/O 6
I/O 3
5
6
5
TXCB
TX1B
I/O 4
I/O 5
I/O 4
RClamp0524P
Figure 10: The connection of the HDMI outputs
Die
Figure 11: Cross-section of exposed thermal pad package
2023-10-25
2
GND
GND1
4
TX1
TMDA Data1+
6
TX1B
TMDA Data1-
8
GND
GND3
10
TXC
TMDA Clock+
12
TXCB
TMDA Clock-
14
Reserv ed
VBUS5V
16
DDC_SDA
SDA
SM5817
D1
18
+5V Power
U4
10
1
TX2
DDC_SCL
I/O 8
I/O 1
I/O 8
9
2
TX2B
DDC_SDA
I/O 7
I/O 2
I/O 7
8
3
GND
GND
GND
GND
GND
7
4
TX1
I/O 6
I/O 3
I/O 6
6
5
TX1B
HPD_HM
I/O 5
I/O 4
I/O 5
RClamp0524P
RClamp0524P
AN-B058
10
DDC_SCL
9
DDC_SDA
8
GND
7
6
HPD_HM
Pin
9