Chrontel CH7515A Podręcznik projektowania układu - Strona 3

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CHRONTEL

T1 (the VCC18 rise slope time) should not be larger than 2ms

The exposed pad, which is the Thermal pad, must be linked to GND.

All the Ferrite Beads described in this document are recommended to have an impedance of less than

0.05 Ohm at DC; 23 Ohm at 25MHz & 47 Ohm at 100MHz. Please refer to Fair Rite part

#2743019447 for details or an equivalent part can be used for the diagram.

2.2

Internal Reference Pins

• RBIAS pin

This pin sets the Band-gap Bias Voltage. A 10 K-Ohm, 1% tolerance resistor should be connected between RBIAS

and GND as shown in Figure 2. A smaller resistance will create less Band-gap Bias voltage. This resistor should be

placed with short and wide traces as near as possible to CH7515A. For optimum performance, this signal should not

overlay the analog power or analog output signals

2.3

General Control Pins

• RB

This pin is the chip reset pin for CH7515A. RB pin, which is internally pulled-up, places the device in the power on

reset condition when this pin is low. As shown in Figure 3, one 10Kohm resistor is necessary to be pulled high to

DVDD (1.8V). One 0.1uf capacitor is recommend to be pulled low to GND. After the powers are stable, please give

the chip the RB signal (low to high) As shown in Figure 1.

Option1: link RB signal to external GPIO_PCH signal (1.8V).

Option2: add the level shifter circuits to link RB signal to GPIO_PCH signal (3.3V).

• XI, XO

27MHz crystal (30ppm) can be connected to these pins of XI, XO as the CH7515A optional reference clock input.

In PCB design, 27MHz crystal must be placed as close as possible to the XI and XO pins, with traces connected from

point to point, overlaying the ground plane. Since the crystal generates timing reference for the CH7515A, it is very

important that noise should not couple into these input pins.

The crystal load capacitance, CL, is usually specified in the crystal spec from the vendor. As an example to show the

load capacitors, Figure 3 shows a reference design for crystal circuit design.

• REFCK

The REFCK is also the optional pin as reference input clock of the CH7515A. The choice is injecting clock 27MHz

(3.3V) at this pin as shown in Figure 3. For PCB design, the capacitor must be placed as close as possible to the

REFCK pin, with traces connected from point to point, overlaying the ground plane.

206-1000-021

Rev 1.0

127

RBIAS

TQFP

CH7515A

Figure 2: RBIAS Pin Connection

2020-07-15

AN-B021

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