Digilent NetFPGA-SUME Podręcznik referencyjny - Strona 5

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NetFPGA-SUME™ Reference Manual

These supply rails are derived from the 12V input (VCC12V0, comes from header J14) using eight high efficiency

switching regulators and one low drop out (LDO) linear regulator from Linear Technology. Since both the DDR3 and

QDRII+ I/O supplies are powered from the VCC1V5 rail, two ferrite beads are also included to prevent high speed

switching noise caused by one memory from affecting the other. Figure 6 shows how the various supplies are

derived from the input.

A Linear Technology LTC6909 is used to generate six out of phase 302 KHz clocks. Each clock is 60 degrees out of

phase with any of the other clock outputs (see Fig. 5). These out of phase clocks are used as the input clocks for the

regulators that produce the high power output supply rails (VCC1V0, VCC1V5, VCC1V8, VCC3V3, and MGTAVCC).

The LTC3839, which produces the VCC1V0 supply rail, is a dual phase converter that directly utilizes the OUT1 clock

and indirectly utilizes the OUT4 clock. The use of out of phase clocks reduces the input RMS ripple current.

Other product and company names mentioned may be trademarks of their respective owners.

Supply Rail

Nominal Voltage

VCC1V0

1.0V

VCC1V8

1.8V

VCC2V0

2.0V

MGTAVCC

1.0V

MGTAVTT

1.2V

VCC3V3

3.3V

VCC1V5

1.5V

MGTVAUX

1.8V

DDRVTT

0.75V

QDRVTT

0.75V

Table 1. Supply rails, voltages, and currents.

Figure 5. LTC6909 clock output phase relationship.

Rated Output Current

40A

15A

+/- 3A

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