Digilent D2-FT Podręcznik referencyjny - Strona 3
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Drukuj stronęD2-FT Reference Manual
Total board current is dependant on FPGA
configuration, clock frequency, and external
connections. In test circuits with roughly 50K
gates routed, a 50MHz clock source, and a
single expansion board attached (the DIO5
board), approximately 200mA +/- 30% of
supply current is drawn from the 1.8V supply,
and approximately 200mA +/- 50% is drawn
from the 3.3V supply. These currents are
strongly dependent on FPGA and peripheral
board configurations.
All FPGA I/O signals use the VCCO voltage
derived from the 3.3V supply. If other VCCO
voltages are required, the regulator output can
be modified by changing R12 according to:
VCCO = 1.25(1 + R12/R11).
Refer to the LM317 data sheet and D2-FT
schematic for further information.
Oscillators
The D2-FT provides a 50MHz SMD primary
oscillator and a socket for a second oscillator.
The primary oscillator is connected to the
GLK2 input of the Spartan 2E (pin B8), and the
secondary oscillator is connected to GCLK3
(pin C8). Both clock inputs can drive the DLL
on the Spartan 2E, allowing for internal
frequencies up to four times higher than the
external clock signals. Any 3.3V oscillator in a
half-size DIP package can be loaded into the
secondary oscillator socket.
Pushbutton and LED
A single pushbutton and LED are provided on
the board allowing basic status and control
functions to be implemented without a
peripheral board. As examples, the LED can
be illuminated from a signal in the FPGA to
verify that configuration has been successful,
and the pushbutton can be used to provide a
basic reset function independent of other
inputs. The circuits are shown in Figure 3.
www.digilentinc.com
Vdd
Push
button
Figure 3. LED and Pushbutton Circuit
Expansion Connectors
The six expansion connectors labeled A1-A2,
B1-B2, and C1-C2 use 2x20 right-angle
headers with100 mil spacing. All six
connectors have GND on pin 1, VU on pin 2,
and 3.3V on pin 3. Pins 4-35 route to FPGA I/O
signals, and pins 36-40 are reserved for JTAG
and/or clock signals. (See Figure 4)
The expansion headers provide 192 signal
connections, and the Spartan 2E-FT256 has
172 available I/O signals. Thus, some FPGA
signals are routed to more than one connector.
The lower 18 pins (pins 4-21) of the A1and B1
connectors are connected to the same 18
FPGA pins, and they are designated as the
"system bus" (a unique chip select signal is
routed to each connector). Other than these 18
shared signals, all remaining FPGA signals are
routed to individual expansion connector
positions.
The lower 18 pins of the A2, B2, and C2
connectors are designated as "peripheral
busses", and each of these busses (named
PA, PB, and PC) use 18 unique signals. The
14 upper pins of each expansion connector
(pins 22-35) have been designated as "module
busses". Each connector has a fully populated
module bus (named MA1, MA2, MB1, MB2,
MC1, and MC2).
System Bus
The "system bus" is a protocol used by certain
expansion boards that mimics a simple 8-bit
microprocessor bus. It uses eight data lines,
six address lines, a write-enable (WE) strobe
that can be used by the peripheral to latch
© Digilent, Inc.
Digilent, Inc.
Pin A12
4.7K
Xilinx
Spartan 2E
4.7K
FT 256
80 Ohm
Pin C15
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