Cisco WS-X6748-GE-TX - Switch - 48 Ports Biała księga - Strona 11
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Scheduling: DWRR
DWRR is a feature that is used on egress (transmit) queues. Explaining DWRR is best served by using an example. Assume a switch port has three
queues. Queue 1 has been given access to 50 percent of the bandwidth, queue 2 has 30 percent, and queue 3 has 20 percent. If the WRR algorithm
is servicing queue 2, and on this service pass it has used 99.9 percent of its allotted bandwidth, the WRR algorithm will still send out the next packet
in the queue as the queue's allotted bandwidth allocation has not yet been used up. When it sends the next packet, it will exceed the amount of
bandwidth that was configured for this queue. Statically over time, queue 2 may end up using a lot more bandwidth than it was initially configured
for when using WRR. (See Figure 12.)
Figure 12. DWRR
DWRR prevents this problem from occurring. If the queue uses more bandwidth than it was allotted, DWRR keeps a tally of the extra bandwidth
used on that pass. On the next pass through the queues, the DWRR algorithm will subtract the extra bandwidth used on the last pass for this turn.
This means statistically over a period of time that each queue will use bandwidth that is much closer to the configured amount for that queue.
Scheduling: SRR
SRR is a recent addition to the scheduling capabilities of the Cisco Catalyst 6500 Family. At the time of writing this paper, support for SRR is only
available on the uplink ports of the Cisco Catalyst 6500 Series Supervisor Engine 32. SRR is different from WRR in that the SRR algorithm
provides a way to shape outbound traffic to a stated rate. In some respects, it is similar to a policer except that traffic in excess of the rate will be
buffered rather than dropped as with a policer.
The shaper is implemented on a per-queue basis and has the effect of smoothing transient bursts of data that pass through that port. SRR also
modifies the way in which it schedules data when compared to the WRR algorithm. This can be seen in Figure 13, which shows a representation
of the packet scheduling order for both algorithms.
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