Yamaha HTR-5860 Instrukcja serwisowa - Strona 29

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Yamaha HTR-5860 Instrukcja serwisowa
IC5 : D60YA003BPYP225 (DSP P.C.B.)

Decoder

No. Name [Default]
1
GP0[4] / (EXT_INT4)
2
GP0[6] / (EXT_INT6)
3
CVDD
4
VSS
5
DVDD
6
GP0[5] / (EXT_INT5)
7
GP0[7] / (EXT_INT7)
8
CLKS1
9
DVDD
10 VSS
11 CVDD
12 TINP1 / AHCLKX0
13 AXR1[11]
14 CVDD
15 VSS
16 CLKX0 / ACLKX0
17 AXR1[12]
18 AXR1[13]
19 ACLKR0
20 DX0
21 FSX0
22 CVDD
23 VSS
24 AFSR0
25 DVDD
26 VSS
27 DR0
28 AHCLKR0
29 CVDD
30 VSS
31 FSX1
32 AXR1[10]
33 CLKX1 / AMUTE0
34 VSS
35 CVDD
36 AXR1[9]
37 DR1 / SDA1
38 AXR1[8]
39 VSS
40 CVDD
EMIF32
L2 Cache/
Memory
4 Banks
McASP1
64K Bytes
Total
McASP0
(4-Way)
McBSP1
McBSP0
L2
I2C1
Enhanced
Memory
DMA
Controller
DA610:
I2C0
(16 channel)
192K Bytes
Timer 1
DA601:
64K Bytes
Timer 0
GP1
GP0
R2 ROM
512K
Bytes
HPI16
Total
I/O
Function
IOZ
General purpose I/O0 port 4 / Interrupt input (polarity selectable individually by using register)
IOZ
General purpose I/O0 port 6 / Interrupt input (polarity selectable individually by using register)
S
1.2V power supply
GND
Ground
S
3.3V power supply
IOZ
General purpose I/O0 port 5 / Interrupt input (polarity selectable individually by using register) (Unconnected)
IOZ
General purpose I/O0 port 7 / Interrupt input (polarity selectable individually by using register) (Unconnected)
I
McBSP1 external clock source
S
3.3V power supply
GND
Ground
S
1.2V power supply
I / IOZ
Timer 1 Input / McASP0 Transmission MCLK
IOZ
McASP1 Transmission/reception data 11
S
1.2V power supply
GND
Ground
IOZ
McBSP0 Transmission clock / McASP0 Transmission BCLK
IOZ
McASP1 Transmission/reception data 12
IOZ
McASP1 Transmission/reception data 13
IOZ
McASP0 Reception BCLK
O/Z
McBSP0 Transmission data
IOZ
McBSP0 Transmission Frame Sync
S
1.2V power supply
GND
Ground
IOZ
McASP0 Reception LRCLK
S
3.3V power supply
GND
Ground
I
McBSP0 Reception data
IOZ
McASP0 Reception MCLK
S
1.2V power supply
GND
Ground
IOZ
McBSP1 Transmission Frame Sync (Input in SPI slave state) (Unconnected)
IOZ
McASP1 Transmission/reception data 10
IOZ
McBSP1 Transmission clock (Input in SPI slave state) / McASP0 MUTE output (Unconnected)
GND
Ground
S
1.2V power supply
IOZ
McASP1 Transmission/reception data 9
I / IOZ
McBSP1 Reception data / I2C1 data (Unconnected)
IOZ
McASP1 Transmission/reception data 8
GND
Ground
S
1.2V power supply
RX-V757/DSP-AX757/DSP-AX757SE
Digital Signal Processors
L1P Cache
Direct Mapped
4K Bytes Total
C67x
TM
CPU
Control
Instruction Fetch
Registers
Instruction Dispatch
Control
Instruction Decode
Logic
Data Path A
Data Path B
Test
A Register File
B Register File
In-Circuit
Emulation
Interrupt
.L1t
.S1t .M1t .D1
.D2 .M2t .S2t .L2t
Control
L1D Cache
2-Way Set
Associative
4K Bytes Total
Clock Generator,
Oscillator and PLL
Power-Down
x4 through x25 Multipliers
Logic
/1 through /32 Dividers
RX-V657/HTR-5860
55