Yamaha DSP-A595a Instrukcja serwisowa - Strona 31

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3 7 63 1515 0
IC14 : LC875164A-5K20
µ
8 bit Sub
-COM
Pin
Pin
Port
No.
Name
1
PA3
CDO
2
PA4
/ICDI
3
PA5
/KM1
4
P70/INT0 LOCKN
5
P71/INT1
ERRD
6
P72/INT2
ERRA
7
P73/INT3 NONPCM
8
/RES
/RES
9
XT1
XT1
10
XT2
XT2
11
VSS1
VSS1
12
CF1
CF1
13
CF2
CF2
14
VDD1
VDD1
15 P80/AN0
NC
16 P81/AN1
NC
17 P82/AN2
NC
18 P83/AN3
NC
19 P84/AN4
NC
20 P85/AN5
NC
TE
L 13942296513
21 P86/AN6
NC
22 P87/AN7
NC
23
P30
/ICAK
24
P31
CEAK
25
P32
/ICAC
26
P33
CEAC2
27
P34
CEAC1
28 P10/SO0
TXAC
29 P11/SI0
RXAC
30 P12/SCK0 CLKAC
31 P13/SO1
RSRV
32 P14/SI1
TRXOB I/O Not used (Normal)
33 P15/SCK1 CLKOB
34 P16/PWM
NC
35 P17/PWM
NC
36
SO2
STM
37
SI2
MTS
38
SCK2
CKIF
39
SI2P3
WCIF
40
PWM1
TRQ
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I/O
Function
I Receive data from DIR2
O Initial clear for DIR2
O Switching DIR2 forced (analog) mode
PLL lock flag
IRQ
DIR 2 error detect
IRQ
AC3D2av mute detect
IRQ
AC3D2av AC-3 data detect
IRQ
– Reset from Main µ-COM
I Connected to VDD1
I Unconnected
G Ground
Ø Ceramic Oscillator Connected (10kHz)
Ø Ceramic Oscillator Connected (10kHz)
+5V power supply
+5V
O Unconnected
O Unconnected
O Unconnected
O Unconnected
O Unconnected
O Unconnected
O Unconnected
O Unconnected
O Initial clear for CODEC AD/DA
O Chip enable for CODEC AD/DA
O Initial clear for AC3D2av
O Chip enable 2 for AC3D2av
O Chip enable 1 for AC3D2av
TX
Transmit data for AC3D2av and CODEC AD/DA
RX Receive data from AC3D2av
Clock for AC3D2av and CODEC AD/DA
CLK
Ipu Not used (Normal)
I Not used (Normal)
I Unconnected
I/O Unconnected
TX Transmit data for Main µ-COM
RX Receive data from Main µ-COM
Clock from Main µ-COM
RXCK
O Clock for Main µ-COM
O Transmit request for Main µ-COM
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2 9
8
Pin
Pin
Port
No.
Name
41
PWM0
NC
42
VDD2
VDD2
43
VSS2
VSS2
44
P00
NC
45
P01
NC
46
P02
NC
47
P03
NC
48
P04
NC
49
P05
NC
50
P06
NC
51
P07
NC
52 P20/INT4
NC
53 P21/INT4
NC
54 P22/INT4
NC
55 P23/INT4
NC
56 P24/INT5
NC
57 P25/INT5
NC
58 P26/INT5
NC
59 P27/INT5
NC
Q Q
60
PB7
NC
3
6 7
1 3
1 5
61
PB6
NC
62
PB5
NC
63
PB4
DSP
64
PB3
MUTO
65
PB2
LDC/O
66
PB1
CDC/O
67
PB0
RF
68
VSS3
VSS3
69
VDD3
VDD3
70
PC7
NC
71
PC6
NC
72
PC5
VER
73
PC4
DRB
74
PC3
DRA
75
PC2
DIC
76
PC1
DIB
77
PC0
DIA
78
PA0
DMT
79
PA1
CLD
80
PA2
CCK
∗1 Digital input selector control
Hi = 1, Low = 0
Input
DIB
DVD/LD
co
TV/DBS
.
9 4
2 8
I/O
Function
OL Unconnected
+5V +5V power supply
G Ground
I/O Unconnected
I/O Unconnected
I/O Unconnected
I/O Unconnected
I/O Unconnected
I/O Unconnected
I/O Unconnected
I/O Unconnected
I/O Unconnected
I/O Unconnected
I/O Unconnected
I/O Unconnected
I/O Unconnected
I/O Unconnected
I/O Unconnected
I/O Unconnected
I/O Unconnected
0 5
8
2 9
9 4
2 8
I/O Unconnected
I/O Unconnected
Ipu Connected to VSS3
Ipu Unconnected (Fixed H)
I LD Coaxial/Optical detect
I Fixed H
Ipu Connected to VSS3 (Switched L)
G Ground
+5V +5V power supply
I/O Unconnected
I/O Unconnected
Ipu Connected to VSS3 (Switched L)
O Unconnected
O Unconnected
O Unconnected
O Digital input selector control B
O Digital input selector control A
O L/R D/A converter mute
O Chip select for DIR2
O Serial clock for DIR2
m
DIA
0
0
1
0
DSP-A595a
9 9
9 9
∗1
∗1
24