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The quick path interconnect (QPI) debug consists of a set of 20 TX lanes plus a CLK and
a set of 20 RX lanes plus a clock. If any one lane fails, the system picks 10 good lanes and
runs in half width. If the clock fails, the system uses one of the data lanes as the CLK and
faildown
runs in half width. This
can run in half width, and the TX port runs in full length. Each CPU has three QPI
interfaces labeled 0, 1, and 2.
In a four-socket or eight-socket system, the QPI meshes all CPUs together, as shown in
Figure 29 and Figure 30.
QPI
QPI
Port 1
Port 1
QPI
QPI
Port 0
Port 0
CPU1
CPU2
QPI
QPI
Port 2
Port 2
Figure 29 Four-socket system QPI topology
QPI
QPI
Port 1
Port 1
QPI
QPI
Port 0
Port 0
CPU5
CPU6
QPI
QPI
Port 2
Port 2
QPI
QPI
Port 1
Port 1
QPI
QPI
Port 0
Port 0
CPU1
CPU2
QPI
QPI
Port 2
Port 2
Figure 30 Eight-socket system QPI topology
happens independently on TX and RX. That is, the RX
QPI
QPI
Port 1
Port 1
QPI
QPI
Four-socket
Port 0
Port 0
QPI topology
CPU3
CPU4
QPI
QPI
Port 2
Port 2
QPI
QPI
Port 1
Port 1
QPI
QPI
Port 0
Port 0
CPU7
CPU8
QPI
QPI
Port 2
Port 2
QPI
QPI
Port 1
Port 1
QPI
QPI
Port 0
Port 0
CPU3
CPU4
QPI
QPI
Port 2
Port 2
Lenovo System x3850 X6 and x3950 X6 Quick Start Guide
Eight-socket
QPI topology
29