Cypress Semiconductor CY7B9911V Arkusz specyfikacji - Strona 4

Przeglądaj online lub pobierz pdf Arkusz specyfikacji dla Sprzęt komputerowy Cypress Semiconductor CY7B9911V. Cypress Semiconductor CY7B9911V 15 stron. Cypress high speed low voltage programmable skew clock buffer specification sheet

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Figure 1
shows the typical outputs with FB connected to a zero skew output.
Figure 1. The Typical Outputs with FB Connected to a Zero Skew Output
1Fx
3Fx
2Fx
4Fx
(N/A)
LM
LL
LH
LM
(N/A)
LH
ML
ML
(N/A)
MM
MM
MH
(N/A)
HL
MH
HM
(N/A)
HH
HL
(N/A)
HM
(N/A)
LL/HH
(N/A)
HH

Test Mode

The TEST input is a three level input. In normal system
operation, this pin is connected to ground, allowing the
CY7B9911V to operate as described in
Description"
on page 3. For testing purposes, any of the three
level inputs can have a removable jumper to ground or be tied
LOW through a 100W resistor. This enables an external tester to
change the state of these pins.
Note
4. FB connected to an output selected for "zero" skew (that is, xF1 = xF0 = MID).
Document Number: 38-07408 Rev. *D
FB Input
REFInput
– 6t
U
– 4t
U
– 3t
U
– 2t
U
– 1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
+6t
U
DIVIDED
INVERT
"Block Diagram
[4]
If the TEST input is forced to its MID or HIGH state, the device
operates with its internal phase locked loop disconnected, and
input levels supplied to REF directly control all outputs. Relative
output-to-output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW), all outputs
function based only on the connection of their own function
select inputs (xF0 and xF1) and the waveform characteristics of
the REF input.
CY7B9911V
3.3V RoboClock+™
Page 4 of 14
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