Cypress Semiconductor CY7C027AV Arkusz specyfikacji - Strona 10
Przeglądaj online lub pobierz pdf Arkusz specyfikacji dla Sprzęt komputerowy Cypress Semiconductor CY7C027AV. Cypress Semiconductor CY7C027AV 19 stron. 3.3v 32k/64k x 16/18 dual-port static ram
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Switching Waveforms
ADDRESS
OE
[24,25]
CE
R/W
DATA OUT
DATA IN
ADDRESS
[24,25]
CE
R/W
DATA IN
Notes
20. R/W must be HIGH during all address transitions.
21. A write occurs during the overlap (t
22. t
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
HA
23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
the bus for the required t
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
SD
24. To access RAM, CE = V
, SEM = V
IL
25. To access upper byte, CE = V
, UB = V
IL
To access lower byte, CE = V
, LB = V
IL
26. Transition is measured ±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
27. During this period, the I/O pins are in the output state, and input signals must not be applied.
28. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
Document #: 38-06078 Rev. *B
(continued)
Figure 7. Write Cycle No. 1: R/W Controlled Timing
t
WC
t
AW
t
t
SA
[26]
t
HZWE
NOTE 27
Figure 8. Write Cycle No. 2: CE Controlled Timing
t
WC
t
AW
t
t
SA
SCE
or t
) of a LOW CE or SEM and a LOW UB or LB.
SCE
PWE
.
IH
, SEM = V
.
IL
IH
, SEM = V
.
IL
IH
CY7C027V/027VN/027AV/028V
[20, 21, 22, 23]
[23]
t
PWE
HA
t
t
SD
[20, 21, 22, 28]
t
HA
t
t
SD
or (t
+ t
) to allow the I/O drivers to turn off and data to be placed on
PWE
HZWE
SD
CY7C037V/037AV/038V
[26]
t
HZOE
t
LZWE
NOTE 27
HD
HD
.
PWE
Page 10 of 18
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