Cypress Semiconductor CY7C037V Arkusz specyfikacji - Strona 13
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Switching Waveforms
CE
Valid First:
L
ADDRESS
L,R
CE
L
CE
R
BUSY
R
CE
Valid First:
R
ADDRESS
L,R
CE
R
CE
L
BUSY
L
Left Address Valid First:
ADDRESS
L
ADDRESS
R
BUSY
R
Right Address Valid First:
ADDRESS
R
ADDRESS
L
BUSY
L
Note
34. If t
is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted.
PS
Document #: 38-06078 Rev. *B
(continued)
Figure 13. Busy Timing Diagram No. 1 (CE Arbitration)
ADDRESS MATCH
t
PS
ADDRESS MATCH
t
PS
Figure 14. Busy Timing Diagram No. 2 (Address Arbitration)
t
or t
RC
WC
ADDRESS MATCH
t
PS
t
BLA
t
or t
RC
WC
ADDRESS MATCH
t
PS
t
BLA
CY7C027V/027VN/027AV/028V
t
t
BLC
BHC
t
t
BLC
BHC
ADDRESS MISMATCH
t
BHA
ADDRESS MISMATCH
t
BHA
CY7C037V/037AV/038V
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