Cypress Semiconductor CY7C1018DV33 Arkusz specyfikacji - Strona 4
Przeglądaj online lub pobierz pdf Arkusz specyfikacji dla Sprzęt komputerowy Cypress Semiconductor CY7C1018DV33. Cypress Semiconductor CY7C1018DV33 9 stron. 1-mbit (128k x 8) static ram
AC Switching Characteristics
Parameter
Read Cycle
[6]
t
V
(typical) to the first access
power
CC
t
Read Cycle Time
RC
t
Address to Data Valid
AA
t
Data Hold from Address Change
OHA
t
CE LOW to Data Valid
ACE
t
OE LOW to Data Valid
DOE
t
OE LOW to Low-Z
LZOE
t
OE HIGH to High-Z
HZOE
t
CE LOW to Low-Z
LZCE
t
CE HIGH to High-Z
HZCE
[9]
t
CE LOW to Power-up
PU
[9]
t
CE HIGH to Power-down
PD
[10, 11]
Write Cycle
t
Write Cycle Time
WC
t
CE LOW to Write End
SCE
t
Address Set-up to Write End
AW
t
Address Hold from Write End
HA
t
Address Set-up to Write Start
SA
t
WE Pulse Width
PWE
t
Data Set-up to Write End
SD
t
Data Hold from Write End
HD
t
WE HIGH to Low-Z
LZWE
t
WE LOW to High-Z
HZWE
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. t
gives the minimum amount of time that the power supply should be at typical V
POWER
7. t
, t
, and t
are specified with a load capacitance of 5 pF as in (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state.
HZOE
HZCE
HZWE
8. At any given temperature and voltage condition, t
9. This parameter is guaranteed by design and is not tested.
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of these
signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
Document #: 38-05465 Rev. *D
Over the Operating Range
Description
[7, 8]
[8]
[7, 8]
[8]
[7, 8]
is less than t
, t
is less than t
HZCE
LZCE
HZOE
[5]
–10 (Industrial)
Min.
100
10
3
0
3
0
10
8
8
0
0
7
5
0
3
values until the first memory access can be performed.
CC
, and t
is less than t
LZOE
HZWE
LZWE
and t
.
HZWE
SD
CY7C1018DV33
Unit
Max.
µs
ns
10
ns
ns
10
ns
5
ns
ns
5
ns
ns
5
ns
ns
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
ns
for any given device.
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