Cypress Semiconductor CY7C1034DV33 Arkusz specyfikacji - Strona 5

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AC Switching Characteristics
[5]
Over the operating range
Parameter
[9, 10]
Write Cycle
t
Write Cycle Time
WC
t
CE Active LOW to Write End
SCE
t
Address Setup to Write End
AW
t
Address Hold from Write End
HA
t
Address Setup to Write Start
SA
t
WE Pulse Width
PWE
t
Data Setup to Write End
SD
t
Data Hold from Write End
HD
t
WE HIGH to Low Z
LZWE
t
WE LOW to High Z
HZWE
Data Retention Characteristics
Over the operating range
Parameter
Description
V
V
for Data Retention
DR
CC
I
Data Retention Current9
CCDR
[11]
t
Chip Deselect to Data Retention Time
CDR
[12]
t
Operation Recovery Time
R
V
CC
CE
Notes
9. The internal write time of the memory is defined by the overlap of CE
to initiate a write and the transition of any of these signals terminates the write. The input data setup and hold timing are referenced to the leading edge of the signal
that terminates the write.
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full device operation requires linear V
Document Number: 001-08351 Rev. *C
(continued)
Description
[3]
[7]
[7]
V
= 2V, CE
CC
CE
< 0.2V, V
2
Figure 3. Data Retention Waveform
DATA RETENTION MODE
3.0V
t
CDR
LOW, CE
1
> 50 μs or stable at V
ramp from V
to V
CC
DR
CC(min)
[3]
Conditions
, CE
> V
– 0.2V,
1
3
CC
> V
– 0.2V or V
< 0.2V
IN
CC
IN
>
V
2V
DR
HIGH, CE
LOW, and WE LOW. Chip enables must be active and WE must be LOW
2
3
and t
.
HZWE
SD
> 50 μs.
CC(min)
CY7C1034DV33
–10
Unit
Min
Max
10
7
7
0
0
7
5.5
0
3
5
Min
Typ
Max
2
25
0
t
RC
3.0V
t
R
Page 5 of 9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
V
mA
ns
ns
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