Cypress Semiconductor CY7C1231H Arkusz specyfikacji - Strona 3

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Pin Definitions

Name
I/O
A
, A
, A
Input-
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge of
0
1
Synchronous
the CLK. A
BW
Input-
Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the
[A:B]
Synchronous
rising edge of CLK.
WE
Input-
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
Synchronous
signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input-
Advance/Load Input. Used to advance the on-chip address counter or load a new address. When
Synchronous
HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address
can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW
in order to load a new address.
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK
is only recognized if CEN is active LOW.
CE
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
1
Synchronous
CE
CE
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
2
Synchronous
CE
CE
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
3
Synchronous
CE
OE
Input-
Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block
Asynchronous
inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave
as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked
during the data portion of a write sequence, during the first clock when emerging from a deselected
state, when the device has been deselected.
CEN
Input-
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM.
Synchronous
When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the
device, CEN can be used to extend the previous cycle when required.
ZZ
Input-
ZZ "sleep" Input. This active HIGH input places the device in a non-time critical "sleep" condition
Asynchronous
with data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin has
an internal pull-down.
DQ
I/O-
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by
s
Synchronous
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by address during the clock rise of the read cycle. The direction of the pins is controlled by OE and
the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQ
the data portion of a write sequence, during the first clock when emerging from a deselected state,
and when the device is deselected, regardless of the state of OE.
DQP
I/O-
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ
[A:B]
Synchronous
sequences, DQP
Mode
Input
Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When
Strap Pin
tied to V
V
Power Supply Power supply inputs to the core of the device.
DD
V
I/O Power
Power supply for the I/O circuitry.
DDQ
Supply
V
Ground
Ground for the device.
SS
NC
–
No Connects. Not Internally connected to the die. 4M, 9M, 18M, 36M, 72M, 144M, 288M, 576M, and
1G are address expansion pins and are not internally connected to the die.
Document #: 001-00207 Rev. *B
are fed to the two-bit burst counter.
[1:0]
, and CE
to select/deselect the device.
2
3
and CE
to select/deselect the device.
1
3
and CE
to select/deselect the device.
1
2
and DQP
are placed in a tri-state condition. The outputs are automatically tri-stated during
s
[A:B]
is controlled by BW
[A:B]
or left floating selects interleaved burst sequence.
DD
Description
correspondingly.
x
CY7C1231H
. During write
s
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