Cypress Semiconductor CY7C1302DV25 Arkusz specyfikacji - Strona 4
Przeglądaj online lub pobierz pdf Arkusz specyfikacji dla Sprzęt komputerowy Cypress Semiconductor CY7C1302DV25. Cypress Semiconductor CY7C1302DV25 19 stron. Cypress 9-mbit burst of two pipelined srams with qdrtm architecture specification sheet
Drukuj stronęSynchronous internal circuitry will automatically three-state
the outputs following the next rising edge of the positive output
clock (C). This will allow for a seamless transition between
devices without the insertion of wait states in a depth
expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the same K clock
rise the data presented to D
[17:0]
Write Data register provided BWS
active. On the subsequent rising edge of the negative input
clock (K), the address is latched and the information presented
to D
is stored into the Write Data register provided
[17:0]
BWS
are both asserted active. The 36 bits of data are then
[1:0]
written into the memory array at the specified location.
When deselected, the Write port will ignore all inputs after the
pending Write operations have been completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1302DV25.
A Write operation is initiated as described in the Write
Operation section above. The bytes that are written are deter-
mined by BWS
and BWS
which are sampled with each set
0
1
of 18-bit data word. Asserting the appropriate Byte Write
Select input during the data portion of a write will allow the data
being presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
38-05625
Single Clock Mode
The CY7C1302DV25 can be used with a single clock mode.
In this mode the device will recognize only the pair of input
clocks (K and K) that control both the input and output
[1]
Application Example
Note:
1. The above application shows 4 QDR-I being used.
Document #: 38-05625 Rev. *A
is latched into the lower 18-bit
are both asserted
[1:0]
registers. This operation is identical to the operation if the
device had zero skew between the K/K and C/C clocks. All
timing parameters remain the same in this mode. To use this
mode of operation, the user must tie C and C HIGH at
power-up.This function is a strap option and not alterable
during device operation.
Concurrent Transactions
The Read and Write ports on the CY7C1302DV25 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the trans-
action on the other port. Also, reads and writes can be started
in the same clock cycle. If the ports access the same location
at the same time, the SRAM will deliver the most recent infor-
mation associated with the specified address location. This
includes forwarding data from a Write cycle that was initiated
on the previous K clock rise.
Depth Expansion
The CY7C1302DV25 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the Positive Input Clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and V
to allow the SRAM to adjust its
SS
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω
=1.5V. The output impedance is adjusted every 1024 cycles to
account for drifts in supply voltage and temperature.
CY7C1302DV25
with V
,
DDQ
Page 4 of 18
[+] Feedback