Cypress Semiconductor CY7C1306BV25 Arkusz specyfikacji - Strona 2
Przeglądaj online lub pobierz pdf Arkusz specyfikacji dla Sprzęt komputerowy Cypress Semiconductor CY7C1306BV25. Cypress Semiconductor CY7C1306BV25 20 stron. Cypress 18-mbit burst of 2 pipelined sram with qdr architecture specification sheet
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Logic Block Diagram (CY7C1303BV25)
D
[17:0]
Address
A
Register
(18:0)
19
K
K
Vref
Control
WPS
Logic
BWS
0
BWS
1
Logic Block Diagram (CY7C1306BV25)
D
[35:0]
Address
A
Register
(17:0)
18
K
K
Vref
Control
WPS
Logic
BWS
0
BWS
1
BWS
2
BWS
3
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
Document #: 38-05627 Rev. *A
18
Write
Data Reg
512Kx18
Memory
Array
CLK
Gen.
Read Data Reg.
36
Write
Data Reg
256Kx36
Memory
Array
CLK
Gen.
Read Data Reg.
Write
Data Reg
Address
Register
512Kx18
Memory
Array
Control
Logic
36
18
Reg.
18
Reg.
Write
Data Reg
Address
Register
256Kx36
Memory
Array
Control
Logic
72
36
Reg.
36
Reg.
CY7C1303BV25-167
CY7C1306BV25-167
167
500
CY7C1303BV25
CY7C1306BV25
A
(18:0)
19
RPS
C
C
18
Reg.
18
Q
[17:0]
18
A
(17:0)
18
RPS
C
C
36
Reg.
36
Q
[35:0]
36
Unit
MHz
mA
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