Cypress Semiconductor CY7C1350G Arkusz specyfikacji

Przeglądaj online lub pobierz pdf Arkusz specyfikacji dla Sprzęt komputerowy Cypress Semiconductor CY7C1350G. Cypress Semiconductor CY7C1350G 16 stron. Cypress 4-mbit (128k x 36) pipelined sram with nobl architecture specification sheet

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Features
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Byte Write capability
• 128K x 36 common I/O architecture
• 3.3V power supply (V
)
DD
• 2.5V/3.3V I/O power supply (V
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable (OE)
• Available in lead-free 100-Pin TQFP package, lead-free
and non-lead-free 119-Ball BGA package
• Burst Capability—linear or interleaved burst order
• "ZZ" Sleep mode option
Logic Block Diagram
A0, A1, A
MODE
CLK
C
CEN
WRITE ADDRESS
ADV/LD
BW
A
BW
B
BW
C
BW
D
WE
OE
CE1
CE2
CE3
ZZ
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05524 Rev. *F
4-Mbit (128K x 36) Pipelined SRAM
)
DDQ
ADDRESS
REGISTER 0
A1
D1
A0
BURST
D0
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 1
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
CONTROL
•
198 Champion Court
with NoBL™ Architecture
Functional Description
The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1350G is equipped with the advanced
No Bus Latency™ (NoBL™) logic required to enable consec-
utive Read/Write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of the SRAM, especially in systems that require
frequent Write/Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which, when deasserted, suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 2.6 ns (250-MHz device)
Write operations are controlled by the four Byte Write Select
(BW
) and a Write Enable (WE) input. All writes are
[A:D]
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
A1'
Q1
A0'
Q0
S
E
N
S
E
MEMORY
WRITE
ARRAY
A
DRIVERS
M
P
S
INPUT
E
REGISTER 1
,
•
San Jose
CA 95134-1709
CY7C1350G
[1]
, CE
, CE
) and an
1
2
3
O
D
U
A
T
P
T
U
A
T
S
B
DQs
U
T
DQP
A
F
E
DQP
B
F
E
DQP
E
C
R
R
DQP
D
I
S
N
E
E
G
INPUT
E
REGISTER 0
•
408-943-2600
Revised July 5, 2006
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