Cypress Semiconductor CY7C1353G Arkusz specyfikacji - Strona 5

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Linear Burst Address Table (MODE = GND)
First
Second
Address
Address
A1, A0
A1, A0
00
01
01
10
10
11
11
00
ZZ Mode Electrical Characteristics
Parameter
I
Sleep mode standby current
DDZZ
t
Device operation to ZZ
ZZS
t
ZZ recovery time
ZZREC
t
ZZ active to sleep current
ZZI
t
ZZ inactive to exit sleep current
RZZI
[2, 3, 4, 5, 6, 7, 8]
Truth Table
Operation
Deselect Cycle
Deselect Cycle
Deselect Cycle
Continue Deselect Cycle
READ Cycle (Begin Burst)
READ Cycle (Continue Burst)
NOP/DUMMY READ (Begin
Burst)
DUMMY READ (Continue Burst)
WRITE Cycle (Begin Burst)
WRITE Cycle (Continue Burst)
NOP/WRITE ABORT (Begin
Burst)
WRITE ABORT (Continue Burst)
IGNORE CLOCK EDGE (Stall)
SLEEP MODE
Notes:
2. X ="Don't Care." H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write
selects are asserted, see truth table for details.
3. Write is defined by BW
, and WE. See truth table for Read/Write.
X
4. When a write cycle is detected, all IOs are tri-stated, even during byte writes.
5. The DQs and DQP
pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
[A:B]
6. CEN = H, inserts wait states.
7. Device powers up deselected and the IOs in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
is inactive or when the device is deselected, and DQs and DQP
Document #: 38-05515 Rev. *E
Third
Fourth
Address
Address
A1, A0
A1, A0
10
11
11
00
00
01
01
10
Description
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Address
Used
CE
CE
CE
1
2
None
H
X
None
X
X
None
X
L
None
X
X
External
L
H
Next
X
X
External
L
H
Next
X
X
External
L
H
Next
X
X
None
L
H
Next
X
X
Current
X
X
None
X
X
= data when OE is active.
[A:B]
Interleaved Burst Address Table
(MODE = Floating or V
First
Second
Address
Address
A1, A0
A1, A0
00
01
01
00
10
11
11
10
Test Conditions
− 0.2V
DD
− 0.2V
DD
ZZ ADV/LD
WE
BW
3
X
L
L
X
H
L
L
X
X
L
L
X
X
L
H
X
L
L
L
H
X
L
H
X
L
L
L
H
X
L
H
X
L
L
L
L
X
L
H
X
L
L
L
L
X
L
H
X
X
L
X
X
X
H
X
X
CY7C1353G
)
DD
Third
Fourth
Address
Address
A1, A0
A1, A0
10
11
11
10
00
01
01
00
Min
Max
40
2t
CYC
2t
CYC
2t
CYC
0
OE
CEN
CLK
X
X
X
L
L->H
Tri-State
X
X
L
L->H
Tri-State
X
X
L
L->H
Tri-State
X
X
L
L->H
Tri-State
X
L
L
L->H Data Out (Q)
X
L
L
L->H Data Out (Q)
X
H
L
L->H
Tri-State
X
H
L
L->H
Tri-State
L
X
L
L->H Data In (D)
L
X
L
L->H Data In (D)
H
X
L
L->H
Tri-State
H
X
L
L->H
Tri-State
X
X
H
L->H
X
X
X
X
Tri-State
= tri-state when OE
[A:B]
Page 5 of 13
Unit
mA
ns
ns
ns
ns
DQ
–
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