Cypress Semiconductor CY7C1365C Arkusz specyfikacji - Strona 5

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Pin Descriptions

Name
TQFP
A0, A1, A
37,36,32,33,34,35,44,45,46,
47,48,49,50,81,82,99,100
92 (for 2 Chip Enable Version)
43 (for 3 Chip Enable Version)
BW
BW
93,94,
A,
B,
95,96
BW
BW
C,
D
GW
88
BWE
87
CLK
89
CE
98
1
CE
97
2
CE
92 (for 3 Chip Enable Version)
3
86
OE
83
ADV
ADSP
84
85
ADSC
ZZ
64
DQs
52,53,56, 57,58,59, 62,63,68,
69,72,73,74,75,78,79,2,3,6,7,
8,9,12,13,18,19,22,23,24,25,
28,29
Document #: 38-05690 Rev. *E
I/O
Input-
Address Inputs used to select one of the 256K address
Synchronous
locations. Sampled at the rising edge of the CLK if ADSP or ADSC
is active LOW, and CE
the 2-bit counter.
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to
Synchronous
conduct Byte Writes to the SRAM. Sampled on the rising edge of
CLK.
Input-
Global Write Enable Input, active LOW. When asserted LOW on
Synchronous
the rising edge of CLK, a global write is conducted (ALL bytes are
written, regardless of the values on BW
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge
Synchronous
of CLK. This signal must be asserted LOW to conduct a Byte Write.
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device.
Also used to increment the burst counter when ADV is asserted LOW,
during a burst operation.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of
Synchronous
CLK. Used in conjunction with CE
device. ADSP is ignored if CE
a new external address is loaded.
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of
Synchronous
CLK. Used in conjunction with CE
device. CE
is sampled only when a new external address is loaded.
2
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of
Synchronous
CLK. Used in conjunction with CE
device. CE
is assumed active throughout this document for BGA.
3
CE
is sampled only when a new external address is loaded.
3
Input-
Output Enable, asynchronous input, active LOW. Controls the
Asynchronous
direction of the I/O pins. When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a Read cycle when
emerging from a deselected state.
Input-
Advance Input signal, sampled on the rising edge of CLK. When
Synchronous
asserted, it automatically increments the address in a burst cycle.
Input-
Address Strobe from Processor, sampled on the rising edge of
Synchronous
CLK, active LOW. When asserted LOW, addresses presented to the
device are captured in the address registers. A
into the burst counter. When ADSP and ADSC are both asserted,
only ADSP is recognized. ASDP is ignored when CE
HIGH.
Input-
Address Strobe from Controller, sampled on the rising edge of
Synchronous
CLK, active LOW. When asserted LOW, addresses presented to the
device are captured in the address registers. A
into the burst counter. When ADSP and ADSC are both asserted,
only ADSP is recognized.
Input-
ZZ "sleep" Input, active HIGH. When asserted HIGH places the
Asynchronous
device in a non-time-critical "sleep" condition with data integrity
preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip
Synchronous
data register that is triggered by the rising edge of CLK. As outputs,
they deliver the data contained in the memory location specified by
the addresses presented during the previous clock rise of the read
cycle. The direction of the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs. When HIGH, DQs are
placed in a tri-state condition.
CY7C1365C
Description
, CE
, and CE
are sampled active. A
1
2
3
and BWE).
[A:D]
and CE
to select/deselect the
2
3
is HIGH. CE
is sampled only when
1
1
and CE
to select/deselect the
1
3
and CE
to select/deselect the
1
2
are also loaded
[1:0]
are also loaded
[1:0]
feed
[1:0]
is deasserted
1
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