Cypress Semiconductor CY7C138 Arkusz specyfikacji - Strona 2

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Pin Configurations

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Table 1. Pin Definitions
Left Port
I/O
I/O
0L–7L(8L)
A
A
0L–11L
0R–11R
CE
CE
L
OE
OE
L
R/W
R/W
L
SEM
SEM
L
INT
INT
L
BUSY
BUSY
L
M/S
V
CC
GND
Table 2. Selection Guide
Description
Maximum Access Time (ns)
Maximum Operating Current
Maximum Standby Current for I
Notes
3. I/O
on the CY7C139.
8R
4. I/O
on the CY7C139.
8L
Document #: 38-06037 Rev. *D
Figure 1. 68-Pin PLCC (Top View)
9 8 7 6
5 4 3 2 1 68
I/O
2L
10
I/O
3L
11
I/O
4L
12
I/O
5L
13
GND
14
I/O
6L
15
I/O
7L
16
V
17
CC
GND
18
I/O
0R
19
I/O
20
1R
I/O
2R
21
V
CC
22
I/O
23
3R
I/O
24
4R
I/O
25
5R
I/O
26
6R
2728 29 30
3132 33 34 35 36 37 38 39 40 41 42 43
Right Port
Data Bus Input/Output
0R–7R(8R)
Address Lines
Chip Enable
R
Output Enable
R
Read/Write Enable
R
Semaphore Enable. When asserted LOW, allows access to eight
R
semaphores. The three least significant bits of the address lines will
determine which semaphore to write or read. The I/O
writing to a semaphore. Semaphores are requested by writing a 0 into the
respective location.
Interrupt Flag. INT
R
when left port reads location FFE. INT
FFF and is cleared when right port reads location FFF.
Busy Flag
R
Master or Slave Select
Power
Ground
7C138-15
7C139-15
Commercial
Commercial
SB1
67
66 65 64 63 62 61
A
60
5L
A
59
4L
A
58
3L
A
57
2L
A
56
1L
A
55
0L
INT
54
53
BUSY
CY7C138/9
GND
52
M/S
51
BUSY
50
49
INT
A
48
0R
47
A
1R
A
46
2R
45
A
3R
A
44
4R
Description
is set when right port writes location FFE and is cleared
L
7C138-25
7C138-35
7C139-25
7C139-35
15
25
220
180
60
40
CY7C138, CY7C139
L
L
R
R
pin is used when
0
is set when left port writes location
R
7C138-55
7C139-55
35
55
160
160
30
30
Page 2 of 17
Unit
ns
mA
mA
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