Cypress Semiconductor Perform STK16C88-3 Podręcznik - Strona 11
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Drukuj stronęSoftware Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows.
Parameter
Alt
t
t
RC
AVAV
[11]
t
t
SA
AVEL
[11]
t
t
CW
ELEH
[7, 11]
t
t
HACE
ELAX
t
RECALL
Switching Waveforms
ADDRESS
t
SA
CE
OE
DQ (DATA)
Notes
11. The software sequence is clocked on the falling edge of CE without involving OE (double clocking will abort the sequence).
12. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
Document Number: 001-50594 Rev. **
[11, 12]
STORE/RECALL Initiation Cycle Time
Address Setup Time
Clock Pulse Width
Address Hold Time
RECALL Duration
Figure 10. CE Controlled Software STORE/RECALL Cycle
t
RC
A
D
D
R
E
S
S
#
1
t
SCE
t
HACE
DATA VALID
Description
t
RC
A
D
D
R
E
S
S
#
6
DATA VALID
STK16C88-3
35 ns
Min
Max
35
0
25
20
20
[12]
t
/ t
STORE
RECALL
HIGH IMPEDANCE
Page 11 of 14
Unit
ns
ns
ns
ns
μs
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