Cypress Semiconductor STK11C68-5 Arkusz specyfikacji - Strona 10
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Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows.
Parameter
Alt
t
t
RC
AVAV
[10]
t
t
AVEL
SA
[10]
t
t
ELEH
CW
[10]
t
t
ELAX
HACE
[10]
t
RECALL
Switching Waveform
ADDRESS
t
SA
CE
OE
DQ (DATA)
Notes
10. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).
11. The six consecutive addresses must be read in the order listed in
Document Number: 001-51001 Rev. *A
[10, 11]
Description
STORE/RECALL Initiation Cycle Time
Address Setup Time
Clock Pulse Width
Address Hold Time
RECALL Duration
Figure 11. CE Controlled Software STORE/RECALL Cycle
t
RC
A
D
D
R
E
S
S
#
1
t
SCE
t
HACE
DATA VALID
Table 1
STK11C68-5 (SMD5962-92324)
35 ns
Min
Max
35
0
25
20
20
t
RC
A
D
D
R
E
S
S
#
6
DATA VALID
on page 4. WE must be HIGH during all six consecutive cycles.
45 ns
55 ns
Min
Max
Min
Max
45
55
0
0
30
35
20
20
20
20
[10]
t
/ t
STORE
RECALL
HIGH IMPEDANCE
Page 10 of 15
Unit
ns
ns
ns
ns
μs
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