Cypress Semiconductor STK12C68-5 Arkusz specyfikacji - Strona 2
Przeglądaj online lub pobierz pdf Arkusz specyfikacji dla Sprzęt komputerowy Cypress Semiconductor STK12C68-5. Cypress Semiconductor STK12C68-5 19 stron. 64 kbit (8k x 8) autostore nvsram
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Pinouts
Figure 1. Pin Diagram - 28-Pin DIP
Pin Definitions
Pin Name
Alt
IO Type
A
–A
Input
0
12
DQ
-DQ
Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.
0
7
Input
WE
W
Input
CE
E
Input
OE
G
V
Ground
SS
V
Power Supply Power Supply Inputs to the Device.
CC
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in
HSB
V
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
CAP
Document Number: 001-51026 Rev. **
Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the
chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
Ground for the Device. The device is connected to ground of the system.
progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A
weak internal pull up resistor keeps this pin high if not connected (connection optional).
to nonvolatile elements.
STK12C68-5 (SMD5962-94599)
Figure 2. Pin Diagram - 28-Pin LLC
Description
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