Cypress Semiconductor STK22C48 Arkusz specyfikacji - Strona 4

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Figure 3. AutoStore Inhibit Mode
Hardware STORE (HSB) Operation
The STK22C48 provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the STK22C48 conditionally initiates a STORE operation
after t
. An actual STORE cycle only begins if a Write to the
DELAY
SRAM takes place since the last STORE or RECALL cycle. The
HSB pin also acts as an open drain driver that is internally driven
LOW to indicate a busy condition, while the STORE (initiated by
any means) is in progress. Pull up this pin with an external 10K
ohm resistor to V
if HSB is used as a driver.
CAP
SRAM Read and Write operations, that are in progress when
HSB is driven LOW by any means, are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
the STK22C48 continues SRAM operations for t
t
, multiple SRAM Read operations take place. If a Write is
DELAY
in progress when HSB is pulled LOW, it allows a time, t
complete. However, any SRAM Write cycles requested after
HSB goes LOW are inhibited until HSB returns HIGH.
During any STORE operation, regardless of how it is initiated,
the STK22C48 continues to drive the HSB pin LOW, releasing it
only when the STORE is complete. After completing the STORE
operation, the STK22C48 remains disabled until the HSB pin
returns HIGH.
If HSB is not used, it is left unconnected.
Hardware RECALL (Power Up)
During power up or after any low power condition (V
V
), an internal RECALL request is latched. When V
RESET
once again exceeds the sense voltage of V
cycle is automatically initiated and takes t
Document Number: 001-51000 Rev. **

Data Protection

The STK22C48 protects data from corruption during low voltage
conditions by inhibiting all externally initiated STORE and Write
operations. The low voltage condition is detected when V
less than V
and WE are low) at power up after a RECALL or after a STORE,
the Write is inhibited until a negative transition on CE or WE is
detected. This protects against inadvertent writes during power
up or brown out conditions.

Noise Considerations

The STK22C48 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between V
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Hardware Protect
The STK22C48 offers hardware protection against inadvertent
STORE operation and SRAM Writes during low voltage condi-
tions. When V
operations and SRAM Writes are inhibited. AutoStore can be
completely disabled by tying VCC to ground and applying +5V to
V
CAP
are only initiated by explicit request using either the software
sequence or the HSB pin.
Low Average Active Power
CMOS technology provides the STK22C48 the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns.
Read or Write cycle time. Worst case current consumption is
shown for both CMOS and TTL input levels (commercial temper-
ature range, VCC = 5.5V, 100% duty cycle on chip enable). Only
standby current is drawn when the chip is disabled. The overall
average current drawn by the STK22C48 depends on the
following items:
. During
DELAY
■
The duty cycle of chip enable
to
DELAY
■
The overall cycle rate for accesses
■
The ratio of Reads to Writes
■
CMOS versus TTL input levels
■
The operating temperature
■
The V
■
IO loading
<
CC
CC
, a RECALL
SWITCH
to complete.
HRECALL
. If the STK22C48 is in a Write mode (both CE
SWITCH
and V
using leads and traces that are as short
CC
SS,
<V
, all externally initiated STORE
CAP
SWITCH
. This is the AutoStore Inhibit mode; in this mode, STOREs
Figure 4
shows the relationship between I
level
CC
STK22C48
is
CC
and
CC
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