EG&G ORTEC 442 Instrukcja obsługi i serwisowania - Strona 10
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Drukuj stronę5.2. BUFFER AMPLIFIER
The restoration circuit is followed by a noninverting
buffer amplifier (Q3-Q6) with a gain of approximately 1.
T h e g a i n
of this stage is given by the r a t i o o f
(RIO + R117)/R1Q. The 442 is dc-coupled from this
stage to the output: so an adjustment is provided in each
stage to adjust its dc level to zero. Potentiometer R7
should be adjusted so that the output dc level of the
buffer amplifier (TP1) is zero volts. The buffer amplifier
drives the input gate and the discriminator.
5.3. INPUT GATE
Transistor Q7 is a shunt-type Input Gate. When the front
panel Mode switch is set at Normal, Q7 remains off until
the peak of the input pulse has been sensed; at the peak
detection, Q7 saturates and clamps the gate of Q8 to
ground. No further input conditions wil l affect the input
circuit until the Q7-Q8 condition
has been restored, and
this prevents positive-on-positive pulse pileup. The Q7-Q8
condition will be reset only after the input signal fal ls
below the discriminator level and the 442 Output pulse
has been completed. The normal timing relations in the
442 are shown in Fig. 5.2, with the Busy Output time
extending from the input peak to the decay of the
Linear Output pulse, and the input gate is automatically
inhibited through this Busy interval. Figure 5.3 shows
pileup rejection of a second input pulse because the
second pulse prevents reset of the discriminator in the
442 until a time after the Linear Output has been
completed, and the Busy interval is extended until the
discriminator has been reset. The internal gating control
is independent of the coincidence or anticoincidence logic
that may also be applied from an external source.
Input Linear Pulse
Disc. Output
Delay Pulse
Width Pulse
Input Gate |normj Q7
Busy Output
Stretch Amp. Output
442 Linear Output
Fig. 5.2. Typical Timing Diagram of 442
in Normal Condition.
OiSG. Lenil
Input Linear Pulses
Disc. Out
Delay Pulse
Width Pulse
Input Gate |norm| Q7
Busy Output
Stretch Amp. Output
442 Linear Output
Fig. 5.3. Typical Timing Diagram of Model 442 Showing
Effect of Eliminating Pulse Pileup.
When the Normal/Gated switch is in the Gated position
and
the
Coinc-Anticoinc
switch
is
in
the
Coinc
position, Q7 will normally be turned on and saturated,
clamping the gate of Q8 to ground. In order to open the
gate by turning off Q7, a logic pulse must be applied to the
Gate Input BNC. This pulse is reshaped to a desired
Gate Period by IC5, Q56, and Q57 and applied to the
input gate drive circuitry (Q41-Q43) to open the gate
(Q7) for the time of the gate period. The gate period must
overlap the peak of the linear pulse in order for the 442 to
function properly.
If the Anticoinc position is selected, Q7 wi l l act in an
inverse manner to its operation in the Coinc mode; Q7 will
normally be off (gate open) except during the gate period,
at which time it will be saturated (gate closed). In order
for the 442 to operate properly in the Anticoinc mode,
the Gate Period pulse must totally overlap the time that the
l inear input is above the discrimination level for the pulse
to be blocked. The range of the Gate Period circuit can be
changed by changing the value of C45.
5.4. BUSY OUTPUT
The Busy Output is a measure of the internally created
dead time of the 442. This signal begins at the peak of the
linear pulse and ends at the completion of the 442 output
pulse if the input is below the discriminator level. Refer
to timing diagrams in Figs. 5.2 and 5.3.