DG TOE10G-IP Manual de configuração - Página 2

Procurar online ou descarregar pdf Manual de configuração para Placa-mãe DG TOE10G-IP. DG TOE10G-IP 18 páginas. Fpga setup with cpu demo

dg_toeudp10gip_fpgasetup_intel.doc

1 Test environment setup when using FPGA and PC

Before running the test, please prepare following test environment.

• FPGA development board: Arria10 SoC/Arria10 GX/Cyclone10 GX/Stratix10 GX (H-Tile)

development board

• PC with 10 Gigabit Ethernet or connecting with 10 Gigabit Ethernet card

• 10Gb Ethernet cable:

a) 10 Gb SFP+ Passive Direct Attach Cable (DAC) which has 1-m or less length

b) 10 Gb SFP+ Active Optical Cable (AOC)

c) 2x10 Gb SFP+ transceivers (10G BASE-R) with optical cable (LC to LC, Multimode)

d) For Stratix10 GX board only, QSFP+ to four SFP+ cable

• micro USB cable for JTAG connection

• Test application provided by Design Gateway for running on Test PC:

TOE10G-IP: "tcpdatatest.exe" and "tcp_client_txrx_40G.exe"

UDP10G-IP: "udpdatatest.exe"

• QuartusII Programmer and NiosII command shell, installed on PC

Note: Example hardware for running the demo is listed as follows.

[1] 10G Network Adapter: Intel X520-DA2

http://www.intel.com/content/www/us/en/network-adapters/converged-network-adapters/

ethernet-x520-server-adapters-brief.html

[2] a) 10-Gigabit SFP+ AOC cable (AOC-S1S1-001)

https://www.10gtek.com/10gsfp+aoc

b) 40-Gigabit QSFP+ to 4x10-Gigabit SFP+ cable

https://www.finisar.com/active-optical-cables/fcbn510qe2cxx

[3] PC: Motherboard ASUS Z170-K, 32 GB RAM, and 64-bit Windows7 OS

26-Aug-20

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