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Intel® Server Platform SR870BH2
1.
Introduction
This document was designed to familiarize the field technician with the error handling
architecture for the Intel® Server Platform SR870BH2 and to provide a quick reference to aid in
the diagnosis of system failures.
It presents an overview of applicable EFI based system Management Utilities (SMU), the
System Error Log (SEL), Machine Check error handling Architecture (MCA) and error
messaging. In additon, many of the error messages have been mapped to a possible point of
failure and will include a brief comment regarding debug methodology.
The document is organized by the following chapters:
1.
Introduction
2.
SEL overview
3.
EFI-Based SEL viewer task
4.
SR870BH2 SEL data tables
5.
SR870BH2 machine check error handling
6.
SR870BH2 PCI device IDs
7.
BIOS POST error codes and messages
8.
Debug methodology and failure isolation
9.
POST codes
10.
Beep codes
11.
Clearing CMOS and BIOS recovery
Revision 1.1
Introduction
1