Dialog Semiconductor SLG46824 Manual de programação - Página 5

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ISPG-SLG46824/6
SLG46824/6
2

Programming Algorithm for NVM Configuration Register Space

The SLG46824 and SLG46826 programming algorithm for the NVM Configuration space consists of a series of I
Write commands, each of which will program one 16 byte page of NVM memory
Data "1" cannot be re-programmed as data "0" without erasure. Each byte can only be programmed one time without erasure.
Note 1: The functionality of the device is based upon the registers. The registers will not be reloaded from the NVM until power is cycled or a reset command is
issued.
The SLG46824 and SLG46826 can be programmed either with or without an acknowledge polling routine. The acknowledge
polling routine is implemented to optimize time sensitive applications that would prefer not to wait the fixed maximum write cycle
time (t
). This method allows the application to know instantly when the NVM write cycle has completed so a subsequent
WR
operation can be started.
Figure 3: Flowchart for Programming NVM without Acknowledge Polling
Control Code = XXXXb
Data = Data + 01H
Block Address = 000b
Word Address = E3H
No
Control Code = XXXXb
Block Address = 010b
Word Address = 00H
Word Address =
Word Address +
10H
No
Revision 1.1
5 of 15
(Note
1).
VDD
POR Delay
Yes
Data = 8EH?
Page Write
Command
Wait 20ms
Sequential
Read for
Verify
No
Data
Correct
Yes
Word
Address
= E0H?
Yes
Done
2
C Sequential
Fail
4-Mar-2019
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