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FMC-PLUS-QSFP-DD User Manual
V1.0 - 20th July 2021
Appendix A: FMC+ Pin Assignments
Appendix A.1: Clock Signals
FMC Signal
GBTCLK0_M2C_P*
GBTCLK1_M2C_P*
GBTCLK2_M2C_P*
GBTCLK3_M2C_P*
GBTCLK4_M2C_P*
GBTCLK5_M2C_P*
Appendix A.2: High Speed Serial IO
FMC Signal
DP0_M2C_P
DP0_M2C_N
DP1_M2C_P
DP1_M2C_N
DP2_M2C_P
DP2_M2C_N
DP3_M2C_P
DP3_M2C_N
DP4_M2C_P
DP4_M2C_N
DP5_M2C_P
DP5_M2C_N
DP6_M2C_P
DP6_M2C_N
DP7_M2C_P
DP7_M2C_N
DP8_M2C_P
DP8_M2C_N
DP9_M2C_P
DP9_M2C_N
FMC+ Pin Assignments
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FMC (J1)
Function
D4
USER_CLK_P
B20
USER_CLK_P
L12
USER_CLK_P
L8
USER_CLK_P
L4
USER_CLK_P
Z20
USER_CLK_P
Table 2 : User Clock Location
FMC (J1)
Function
C6
QSFP_0_RX_P0 | QSFP_0_TX_P0
C7
QSFP_0_RX_N0 | QSFP_0_TX_N0
A2
QSFP_0_RX_P1 | QSFP_0_TX_P1
A3
QSFP_0_RX_N1 | QSFP_0_TX_N1
A6
QSFP_0_RX_P2 | QSFP_0_TX_P2
A7
QSFP_0_RX_N2 | QSFP_0_TX_N2
A10
QSFP_0_RX_P3 | QSFP_0_TX_P3
A11
QSFP_0_RX_N3 | QSFP_0_TX_N3
A14
QSFP_0_RX_P4 | QSFP_0_TX_P4
A15
QSFP_0_RX_N4 | QSFP_0_TX_N4
A18
QSFP_0_RX_P5 | QSFP_0_TX_P5
A19
QSFP_0_RX_N5 | QSFP_0_TX_N5
B16
QSFP_0_RX_P6 | QSFP_0_TX_P6
B17
QSFP_0_RX_N6 | QSFP_0_TX_N6
B12
QSFP_0_RX_P7 | QSFP_0_TX_P7
B13
QSFP_0_RX_N7 | QSFP_0_TX_N7
B8
QSFP_1_RX_P0 | QSFP_1_TX_P0
B9
QSFP_1_RX_N0 | QSFP_1_TX_N0
B4
QSFP_1_RX_P1 | QSFP_1_TX_P1
B5
QSFP_1_RX_N1 | QSFP_1_TX_N1
Table 3 : Serial Channel Locations (continued on next page)
|
Function
|
USER_CLK_N
|
USER_CLK_N
|
USER_CLK_N
|
USER_CLK_N
|
USER_CLK_N
|
USER_CLK_N
|
Function
FMC (J1)
FMC Signal
D5
GBTCLK0_M2C_N*
B21
GBTCLK1_M2C_N*
L13
GBTCLK2_M2C_N*
L9
GBTCLK3_M2C_N*
L5
GBTCLK4_M2C_N*
Z21
GBTCLK5_M2C_N*
FMC (J1)
FMC Signal
C2
DP0_C2M_P
C3
DP0_C2M_N
A22
DP1_C2M_P
A23
DP1_C2M_N
A26
DP2_C2M_P
A27
DP2_C2M_N
A30
DP3_C2M_P
A31
DP3_C2M_N
A34
DP4_C2M_P
A35
DP4_C2M_N
A38
DP5_C2M_P
A39
DP5_C2M_N
B36
DP6_C2M_P
B37
DP6_C2M_N
B32
DP7_C2M_P
B33
DP7_C2M_N
B28
DP8_C2M_P
B29
DP8_C2M_N
B24
DP9_C2M_P
B25
DP9_C2M_N
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