EPC EPC9079 Manual de início rápido - Página 2
Procurar online ou descarregar pdf Manual de início rápido para Placa-mãe EPC EPC9079. EPC EPC9079 6 páginas. 200 v half-bridge with gate drive, using epc2046
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QUICK START GUIDE
DESCRIPTION
The EPC9079 development board (figure 1) is a 200 V maximum device
voltage, 6 A maximum output current, half bridge with onboard gate
drives, featuring two EPC2046 enhancement mode (eGaN®) field effect
transistors (FETs). The purpose of this development board is to simplify
the evaluation process of the EPC2046 eGaN FETs by including all the
critical components on a single board that can be easily connected into
any existing converter.
The EPC9079 development board is 1.5" x 2" and contains two EPC2046
eGaN FETs in a half bridge configuration. As supplied, the high side gate
drive uses a digital isolator and both FETs use the Texas Instruments
UCC27611 gate driver. The board also contains all critical components
and layout for optimal switching performance. There are also various
probe points to facilitate simple waveform measurement and efficiency
calculation, as well as the option to add trimmer resistors for adjustable
deadtime, to provide separate high and low side inputs, and to add an
isolator for the low side gate drive. A block diagram of the circuit is given
in figure 2.
For more information on the EPC2046 please refer to the datasheet
available from EPC at www.epc-co.com. The datasheet should be read in
conjunction with this quick start guide.
QUICK START PROCEDURE
Development board EPC9079 is easy to set up to evaluate the
performance of EPC2046 eGaN FETs. Refer to figure 3 for proper connect
and measurement setup and follow the procedure below:
1. With power off, connect the input power supply bus to +VIN (J5, J6)
and ground / return to –VIN (J7, J8).
2. With power off, connect the switch node (SW) of the half bridge OUT
(J3, J4) to your circuit as required (half bridge configuration).
3. With power off, connect the gate drive power supply to +VDD
(J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power off, connect the input PWM control signal to PWM
(J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7.5 V
and 12 V range.
6. Turn on the controller / PWM input source.
7. Turn on the bus voltage to the required value (do not exceed the
absolute maximum voltage) and probe switching node to see
switching operation.
8. Once operational, adjust the PWM control, bus voltage, and load within
the operating range and observe the output switching behavior,
efficiency and other parameters.
9. For shutdown, please follow steps in reverse.
2 |
Table 1: Performance Summary (T
Symbol
V
DD
V
IN
I
OUT
V
PWM
(1) Maximum input voltage depends on inductive loading, maximum switch node ringing must be kept
under 200 V for EPC2046.
(2) Maximum current depends on die temperature – actual maximum current with be subject to
switching frequency, bus voltage and thermal cooling.
(3) Limited by time needed to 'refresh' high side bootstrap supply voltage.
NOTE. When measuring the high frequency content switch node, care must be taken
to provide an accurate high speed measurement. An optional two pin header (SWP1) is
included for switch node measurement. It is recommended to install measurement point on
backside of board to prevent contamination of the top side components.
For information about measurement techniques, please review the how to GaN series:
HTG09- Measurement
http://epc-co.com/epc/DesignSupport/TrainingVideos/HowtoGaN/
| EPC – EFFICIENT POWER CONVERSION CORPORATION |
= 25°C) EPC9079
A
Parameter
Conditions
Gate Drive Input Supply Range
Bus Input Voltage Range
(1)
Switch Node Output Current
(2)
PWM Logic Input Voltage
Input 'High'
Threshold
Input 'Low'
Minimum 'High' State
V
PWM
Input Pulse Width
fall time < 10ns
Minimum 'Low' State Input
V
PWM
Pulse Width
fall time < 10ns
(3)
Figure 1: EPC9079 development board
WWW.EPC-CO.COM
EPC9079
Min
Max Units
7.5
12
V
160
V
6
A
3.5
6
V
0
1.5
V
rise and
50
ns
rise and
50
ns
| COPYRIGHT 2017