Digilent Nexys2 Manual de referência - Página 14
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Nexys2 Reference Manual
VDHL source code is available in a reference design posted on the Digilent website to illustrate the
use of these devices. A base system builder file is also available for using these devices with Xilinx's
EDK tool and MicroBlaze processor core, both available from Xilinx. Complete information is available
for both devices from the manufacturer websites.
ADDR0: NA
ADDR1: J1
ADDR2: J2
ADDR3: H4
ADDR4: H1
ADDR5: H2
ADDR6: J5
ADDR7: H3
Copyright Digilent, Inc.
Figure 22: Nexys2 memory circuits
Table 2: Memory Address and Data Bus Pin Assignments
Address signals
ADDR8: H6
ADDR9: F1
ADDR10: G3
ADDR11: G6
ADDR12: G5
ADDR13: G4
ADDR14: F2
ADDR15: E1
ADDR16: M5
DATA0: L1
ADDR17: E2
DATA1: L4
ADDR18: C2
DATA2: L6
ADDR19: C1
DATA3: M4
ADDR20: D2
DATA4: N5
ADDR21: K3
DATA5: P1
ADDR22: D1
DATA6: P2
ADDR23: K6
DATA7: R2
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Digilent
www.digilentinc.com
Data signals
DATA8: L3
DATA9: L5
DATA10: M3
DATA11: M6
DATA12: L2
DATA13: N4
DATA14: R3
DATA15: T1
Doc: 502-134