AKM AKD4127-A Manual - Página 3

Procurar online ou descarregar pdf Manual para Placa-mãe AKM AKD4127-A. AKM AKD4127-A 20 páginas. Ak4127 evaluation board rev.0

Imprimir página
ASAHI KASEI
(2) All clocks are fed through the 10pin port
When using PORT2 (INPUT), nothing should be connected to J1 (COAX) and PORT1 (DIR).
• SW3 setting (See Table 2)
Upper-side is "H" and lower-side is "L".
SW3 No.
1
2
3
4
5
6
7
Mode
Master / Slave
0
1
Slave
2
IMCLK = DVSS
3
IBICK = Input
4
ILRCK = Input
5
6
7
8
9
10
Master
11
IMCLK = Input
IBICK = Output
12
ILRCK = Output
13
14
15
Note 1. PLL lock rage is changed by the value of R and C connected FILT pin. Refer to "PLL Loop Filter" in the
datasheet. 470Ω, 0.22µF and 1nF are implemented on the evaluation board.
Note 2. The IBCIK must be continuous except when the clocks are changed.
Note 3. IBCIK = 32fsi is supported only 16bit LSB justified and I
Note 4. Refer to "Soft Mute Operation" for Manual mode and Semi-Auto mode in the datasheet.
<KM085601>
JP2
IBICK
Name
ON ("H")
DITH
Dither ON
PLL2
PLL1
PLL0
IDIF0
AK4127 Audio I/F Format Setting
IDIF1
IDIF2
Table 2. SW3 Setting
PLL2
PLL1
PLL0
L
L
L
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
H
H
L
H
H
H
L
L
L
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
H
H
L
H
H
H
Table 3. PLL Setting (Input PORT)
JP3
JP4
SDTI
ILRCK
OFF ("L")
Dither OFF
PLL Mode Setting
Refer to Table 3
Refer to Table 4
ILRCK Freq
IBICK Freq
8k ∼ 96kHz
8k ∼ 216kHz
Depending on
16k ∼ 216kHz
IDIF2-0
(Note 1)
32fsi (Note 3)
8k ∼ 216kHz
(Note 2)
8k ∼ 216kHz
8k ∼ 108kHz
8k ∼ 54kHz
8k ∼ 216kHz
8k ∼ 216kHz
8k ∼ 108kHz
8k ∼ 54kHz
8k ∼ 216kHz
2
S Compatible.
- 3 -
[AKD4127-A]
Default
L
H
L
H
L
H
L
IMCLK
Not
needed.
Semi-Auto
Reserved
64fsi
Not
needed.
128fsi
64fsi
Semi-Auto
128fs
256fs
512fs
128fs
Semi-Auto
64fs
192fs
384fs
768fs
192fs
Semi-Auto
SMUTE
(Note 4)
Manual
Manual
Manual
Manual
2006/11