Cypress CE219490 Manual do utilizador - Página 6

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LUT#

LUT2

Sequential (gated) output

LUT3

Sequential (gated) output

LUT4

Combinatorial output

Figure 6

and

Figure 7

show the Peripheral-Clock configuration for Smart I/O and TCPWM resources respectively.

Reusing This Example

This example is designed for the

project and choose Change Device. If changing to a different kit, you may need to reassign pins.

CY8CKIT-062-BLE

CY8CKIT-062-WiFi-BT

CY8CPROTO-062-4343W

www.cypress.com

Table 3. Smart I/O LUT Configuration

Mode

LUT inputs

TR2

LUT2

LUT3

Figure 6. Peripheral-Clock Configuration for Smart I/O

Figure 7. Peripheral-Clock Configuration for TCPWM

supported

kits. To port the design to a different PSoC 6 MCU device, right-click an application

Table 4. Device and Pin Mapping Table across PSoC 6 MCU Kits

Kit Name

Document No. 002-25568 Rev.*A

LUT

Output

Mapping

TR1

TR0

LUT2

0x01

LUT2

0x81

Chip 4

0x42

Device Used

CY8C6347BZI-BLD53

CY8C6247BZI-D54

CY8C624ABZI-D44

PSoC 6 MCU Ramping LED using Smart I/O

Description

Implements a logic NOT operation

Implements a logic XNOR operation

Implements a logic XOR operation

LED

P13[7]