Cypress S6J3200 Series Manuallines - Página 5

Procurar online ou descarregar pdf Manuallines para Microcontroladores Cypress S6J3200 Series. Cypress S6J3200 Series 9 páginas.

Imprimir página

these two traces becomes unbalanced, and some of the energy in the signal gets converted to common-mode. This

conversion should be avoided wherever possible for the following reasons:

▪

Common-mode energy radiates as EMI

▪

Common-mode noise couples as crosstalk to nearby signals

▪

Imbalance causes a reduction in differential signal integrity

As noted in

Table

balanced pair (L

these transmission lines (typically 400 ps), and remains the same regardless of the signaling rate.

While there appears to be a significant signal length mismatch (L

the routing to one connector only shows a part of the transmission line. Because there is often a second connector at

the other end of the cable, the exit-routing of that connector may be used to compensate for the entry-routing to a

local connector. When measuring L

(S6J3200) and the pins of the receiving device (normally a display), and not just with the local connector.

The recommendation in

FPD-Link interface. The L

the clock and data signals. With a TxCLK± of 50 MHz, each data line carries 350 Mbps of video; the unit interval (UI)

of this data is 2.85 ns. At this signaling rate, a 50-ps offset is less than 0.02 UI, and reduces the link timing margin by

less than 2%. At slower signaling rates, larger L

setup and hold requirements at the display end of the FPD-Link interface.

3.4

Trace Routing Limitations

Do not use 90-degree bends when routing traces; instead, use 45-degree angles or curves because Sharp bends

have additional capacitance between the traces, which causes a change in the transmission line impedance.

shows trace routing recommendations.

3.5

Layout of Power and Ground

Power and ground traces should be as short and wide as reasonably possible. Power for the FPD-Link should be

isolated from other power domains of the regulator. Put bypass capacitors near power / ground pins.

a layout of power and ground.

www.cypress.com

1, Cypress recommends limiting the mismatch between true and complement signals within a

) to no more than 5 mm or 50 ps. This limitation is based on the rise / fall time of the signals on

, the total mismatch in length is between the pins of the sending device

Table 1

for L

is also 5 mm (50 ps), but this is for operation at the 50-MHz clock rate of the

mismatch causes an increase in the transmit pulse position offset (TPPOS) by offsetting

Figure 5. Trace Routing Recommendations

90°

Right Angle

Document No. 002-11139 Rev. *A

FPD-Link PCB Guidelines for the Traveo Family S6J3200 Series MCUs

) between the TxDOUTy± and TxDOUTz± signals,

offsets are usually acceptable so long as the interface meets the

Bend / Curve

Obtuse Angle

≥135°

Figure 6

Figure 5

shows