Cypress 7C185-35 Ficha de especificações - Página 5

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Switching Waveforms

[10,11]
Read Cycle No.1
ADDRESS
DATA OUT
PREVIOUS DATA VALID
[12,13]
Read Cycle No.2
CE
1
CE
2
OE
OE
HIGH IMPEDANCE
DATA OUT
V
CC
SUPPLY
CURRENT
Write Cycle No. 1 (WE Controlled)
ADDRESS
CE
1
CE
CE
2
WE
OE
DATA I/O
10. Device is continuously selected. OE, CE
11. WE is HIGH for read cycle.
12. Data I/O is High Z if OE = V
13. The internal write time of the memory is defined by the overlap of CE
to initiate write. A write can be terminated by CE
rising edge of the signal that terminates the write.
14. During this period, the I/Os are in the output state and input signals should not be applied.
Document #: 38-05043 Rev. *A
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
50%
[11,13]
t
AW
t
SA
NOTE 14
t
HZOE
= V
. CE
= V
.
1
IL
2
IH
, CE
= V
, WE = V
, or CE
=V
IH
1
IH
IL
2
or WE going HIGH or CE
1
t
RC
t
RC
DATA VALID
t
WC
t
SCEI
t
SCE2
t
PWE
t
SD
DATA
VALID
IN
.
IL
LOW, CE
HIGH and WE LOW. CE
1
2
going LOW. The data input set-up and hold timing should be referenced to the
2
CY7C185
DATA VALID
t
HZOE
t
HZCE
IMPEDANCE
t
PD
50%
t
HA
t
HD
and WE must be LOW and CE
must be HIGH
1
2
HIGH
ICC
ISB
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