Cypress Semiconductor CY25822-2 Ficha de especificações - Página 4

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Table 4. Spread Spectrum Select (continued)
SS3
SS2
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
Byte 1: Control Register
Bit
@Pup
7
1
6
1
5
0
4
0
3
1
2
1
1
0
0
0
Bytes 2 through 5: Reserved Registers
Byte 6: Vendor/Revision ID Register
Bit
@Pup
Pin#
Name
7
0
–
6
0
–
5
0
–
4
0
–
3
1
–
2
0
–
1
0
–
0
0
–
Document #: 38-07531 Rev. **
SS1
SS0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Pin#
Name
5
REFEN
5
REFSLEW
Not Applicable
Not Applicable
4
CLKSLEW
4
CLKEN
Not Applicable
Not Applicable
Pin Description
–
Revision ID Bit 3
–
Revision ID Bit 2
–
Revision ID Bit 1
–
Revision ID Bit 0
–
Vendor ID Bit 3
–
Vendor ID Bit 2
–
Vendor ID Bit 1
–
Vendor ID Bit 0
Spread Mode
Down
Down
Down
Center
Center
Center
Center
Center
Center
Center
Center
Pin Description
REFOUT enable
0 = disabled, 1 = enabled
REFOUT edge rate control
0 = slow, 1 = nominal
Reserved.
Reserved
CLKOUT edge rate control
0 = slow, 1 = nominal
CLKOUT enable
0 =disabled, 1 = enabled
Reserved
Reserved
PWRDWN# (Power-down) Clarification
The PWRDWN# (Power-down) pin is used to shut off ALL
clocks prior to shutting off power to the device. PWRDWN# is
an asynchronous active LOW input. This signal is synchro-
nized internally to the device powering down the clock synthe-
sizer. PWRDWN# is an asynchronous function for powering up
the system. When PWRDWN# is low, all clocks are driven to
a LOW value and held there and the VCO and PLLs are also
powered down. All clocks are shut down in a synchronous
manner so has not to cause glitches while transitioning to the
low 'stopped' state. When PWRDWN# is deasserted the
clocks should remain stopped until the VCO is stable and
within specification (t
STABLE
tri-stated or driven low depending on the state of the tri-state
2
enable I
C register bit. CY25822 clocks that are stopped in the
driven state are driven low.
The CLKIN input must be on and within specified operating
parameters before PWRDWN# is asserted and it must remain
in this state while PWRDWN# is asserted.
CY25822-2
Spread Amount%
2.0
2.5
3.0
±0.3
±0.4
±0.5
±0.6
±0.8
±1.0
±1.25
±1.5
). A stopped clock is either
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