Cypress Semiconductor CY7B9910 Ficha de especificações - Página 2

Procurar online ou descarregar pdf Ficha de especificações para Hardware informático Cypress Semiconductor CY7B9910. Cypress Semiconductor CY7B9910 12 páginas. Cypress low skew clock buffer specification sheet

Pin Configuration

Pin Definitions

Signal Name
IO
REF
I
Reference frequency input.This input supplies the frequency and timing against which all functional
variations are measured.
FB
I
PLL feedback input (typically connected to one of the eight outputs).
[1,2,3]
FS
I
Three level frequency range select.
TEST
I
Three level select. See
Q[0..7]
O
Clock outputs.
V
PWR
Power supply for output drivers.
CCN
V
PWR
Power supply for internal circuitry.
CCQ
GND
PWR
Ground.

Test Mode

The TEST input is a three level input. In normal system operation, this pin is connected to ground, allowing the CY7B9910 and
CY7B9920 to operate as described in
removable jumper to ground or be tied LOW through a 100W resistor. This enables an external tester to change the state of these pins.
If the TEST input is forced to its MID or HIGH state, the device operates with its internal phase locked loop disconnected and input
levels supplied to REF directly control all outputs. Relative output-to-output functions are the same as in normal mode.
Notes
1. For all three state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
circuitry holds an unconnected input to VCC/2.
2. The level to be set on FS is determined by the "normal" operating frequency (fNOM) of the VCO (see
and FB inputs are fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs are fNOM/X when the device is configured for a
frequency multiplication by using external division in the feedback path of value X.
3. When the FS pin is selected HIGH, the REF input must not transition upon power up until VCC reached 4.3V.
Document Number: 38-07135 Rev. *B
SOIC
Top View
REF
1
V
2
CCQ
FS
3
NC
4
V
5
CCQ
V
6
CCN
7B9910
Q0
7B9920
7
Q1
8
GND
9
Q2
10
Q3
11
V
12
CCN
TEST
MODE.
Block Diagram
Description. For testing purposes, any of the three level inputs can have a
24
GND
TEST
23
22
NC
21
GND
20
V
CCN
19
Q7
18
Q6
GND
17
16
Q5
15
Q4
V
14
CCN
FB
13
Description
Logic Block
Diagram). The frequency appearing at the REF
CY7B9910
CY7B9920
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