Cypress Semiconductor CY7B992 Ficha de especificações - Página 15

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SYSTEM
CLOCK
Figure 8
shows the CY7B991 and 992 connected in series to construct a zero skew clock distribution tree between boards. Delays
of the downstream clock buffers are programmed to compensate for the wire length (that is, select negative skew equal to the wire
delay) necessary to connect them to the master clock source, approximating a zero delay clock tree. Cascaded clock buffers accumu-
lates low frequency jitter because of the non-ideal filtering characteristics of the PLL filter. Do not connect more than two clock buffers
in series.
Document Number: 38-07138 Rev. *B
Figure 8. Board-to-Board Clock Distribution
REF
FB
REF
FS
4Q0
4F0
4Q1
4F1
3Q0
3F0
3Q1
3F1
2F0
2Q0
2F1
2Q1
1F0
1Q0
1F1
1Q1
TEST
Z
0
L1
L2
Z
0
L3
Z
0
L4
FB
REF
FS
4Q0
4F0
Z
4Q1
0
4F1
3Q0
3F0
3Q1
3F1
2F0
2Q0
2F1
2Q1
1F0
1Q0
1F1
1Q1
TEST
CY7B991
CY7B992
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