Cypress Semiconductor CY7C1223H Ficha de especificações - Página 10

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Switching Characteristics

Parameter
t
V
(Typical) to the first Access
POWER
DD
Clock
t
Clock Cycle Time
CYC
t
Clock HIGH
CH
t
Clock LOW
CL
Output Times
t
Data Output Valid After CLK Rise
CO
t
Data Output Hold After CLK Rise
DOH
t
Clock to Low-Z
CLZ
t
Clock to High-Z
CHZ
t
OE LOW to Output Valid
OEV
t
OE LOW to Output Low-Z
OELZ
t
OE HIGH to Output High-Z
OEHZ
Set-up Times
t
Address Set-up Before CLK Rise
AS
t
ADSC, ADSP Set-up Before CLK Rise
ADS
t
ADV Set-up Before CLK Rise
ADVS
t
GW, BWE, BW
WES
t
Data Input Set-up Before CLK Rise
DS
t
Chip Enable Set-up Before CLK Rise
CES
Hold Times
t
Address Hold After CLK Rise
AH
t
ADSP , ADSC Hold After CLK Rise
ADH
t
ADV Hold After CLK Rise
ADVH
t
GW,BWE, BW
WEH
t
Data Input Hold After CLK Rise
DH
t
Chip Enable Hold After CLK Rise
CEH
Notes:
10. This part has a voltage regulator internally; tpower is the time that the power needs to be supplied above V
can be initiated.
11. t
, t
, t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ
CLZ
OELZ
OEHZ
12. At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
13. This parameter is sampled and not 100% tested.
14. Timing reference level is 1.5V when V
15. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05674 Rev. *B
Over the Operating Range
Description
[10]
[11, 12, 13]
[11, 12, 13]
[11, 12, 13]
[11, 12, 13]
Set-up Before CLK Rise
[A:B]
Hold After CLK Rise
[A : B]
is less than t
and t
is less than t
OEHZ
OELZ
CHZ
= 3.3V and 1.25V when V
= 2.5V.
DDQ
DDQ
[14, 15]
166 MHz
Min.
Max.
1
6.0
2.5
2.5
3.5
1.5
0
3.5
3.5
0
3.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
minimum initially before a read or write operation
DD
to eliminate bus contention between SRAMs when sharing the same
CLZ
CY7C1223H
133 MHz
Min.
Max.
Unit
1
ms
7.5
ns
3.0
ns
3.0
ns
4.0
ns
1.5
ns
0
ns
4.0
ns
4.0
ns
0
ns
4.0
ns
1.5
ns
1.5
ns
1.5
ns
1.5
ns
1.5
ns
1.5
ns
0.5
ns
0.5
ns
0.5
ns
0.5
ns
0.5
ns
0.5
ns
Page 10 of 16
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