Cypress Semiconductor CY7C130 Ficha de especificações - Página 7
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Switching Characteristics
Parameter
Busy/Interrupt Timing
t
BUSY LOW from Address Match
BLA
t
BUSY HIGH from Address Mismatch
BHA
t
BUSY LOW from CE LOW
BLC
t
BUSY HIGH from CE HIGH
BHC
t
Port Set Up for Priority
PS
[18]
t
R/W LOW after BUSY LOW
WB
t
R/W HIGH after BUSY HIGH
WH
t
BUSY HIGH to Valid Data
BDD
t
Write Data Valid to Read Data Valid
DDD
t
Write Pulse to Data Delay
WDD
Interrupt Timing
t
R/W to INTERRUPT Set Time
WINS
t
CE to INTERRUPT Set Time
EINS
t
Address to INTERRUPT Set Time
INS
t
OE to INTERRUPT Reset Time
OINR
t
CE to INTERRUPT Reset Time
EINR
t
Address to INTERRUPT Reset Time
INR
Shaded areas contain preliminary information.
Notes
17. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
18. CY7C140/CY7C141 only.
19. A write operation on Port A, where Port A has priority, leaves the data on Port B's outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B's address is toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
Document #: 38-06002 Rev. *E
Over the Operating Range
Description
[17]
[17]
[17]
[17]
[17]
[7, 12]
(continued)
7C130-25
[4]
7C131-15
7C131-25
7C131A-15
7C140-25
7C141-15
7C141-25
Min
Max
Min
15
15
15
15
5
5
0
0
13
20
15
Note 19
Note 19
Note 19
Note 19
15
15
15
15
15
15
CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
7C130-30
[4]
7C130A-30
7C131-30
Unit
7C140-30
7C141-30
Max
Min
Max
20
20
ns
20
20
ns
20
20
ns
20
20
ns
5
ns
0
ns
30
ns
25
30
ns
Note 19
ns
Note 19
ns
25
25
ns
25
25
ns
25
25
ns
25
25
ns
25
25
ns
25
25
ns
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