Cypress Semiconductor CY7C1302DV25 Ficha de especificações - Página 18

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Document History Page
Document Title:CY7C1302DV25 9-Mb Burst of 2 Pipelined SRAM with QDR™ Architecture
Document Number: 38-05625
REV.
ECN NO.
Issue Date
**
253010
See ECN
*A
436864
See ECN
Document #: 38-05625 Rev. *A
Orig. of
Change
SYT
New Data Sheet
NXR
Converted from Preliminary to Final
Removed 133 MHz & 100 MHz from product offering
Included the Industrial Operating Range.
Changed C/C Description in the Features Section & Pin Description Table
Changed t
from 100 ns to 50 ns, changed t
TCYC
changed t
and t
TH
TL
table
Modified the ZQ pin definition as follows:
Alternately, this pin can be connected directly to V
minimum impedance mode
Included Maximum Ratings for Supply Voltage on V
Changed the Maximum Ratings for DC Input Voltage from V
Modified the Description of I
Current on page # 13
Modified test condition in note# 14 from V
Updated the Ordering Information table and replaced the Package Name
Column with Package Diagram
CY7C1302DV25
Description of Change
from 10 MHz to 20 MHz and
TF
from 40 ns to 20 ns in TAP AC Switching Characteristics
from Input Load current to Input Leakage
X
< V
DDQ
, which enables the
DDQ
Relative to GND
DDQ
to V
DDQ
DD
≤ V
to V
DD
DDQ
DD
Page 18 of 18
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