Cypress Semiconductor CY7C1302DV25 Ficha de especificações - Página 2

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Selection Guide

Maximum Operating Frequency
Maximum Operating Current

Pin Configuration

1
2
A
NC
Gnd/144M NC/36M
B
NC
Q9
C
NC
NC
D
NC
D11
E
NC
NC
F
NC
Q12
G
NC
D13
H
NC
VREF
J
NC
NC
K
NC
NC
L
NC
Q15
M
NC
NC
N
NC
D17
P
NC
NC
R
TDO
TCK

Pin Definitions

Name
I/O
D
Input-
[17:0]
Synchronous
WPS
Input-
Synchronous
BWS
,
Input-
0
BWS
Synchronous
1
A
Input-
Synchronous
Q
Outputs-
[17:0]
Synchronous
RPS
Input-
Synchronous
Document #: 38-05625 Rev. *A
165-ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1302DV25 (512K x 18)
3
4
5
WPS
BWS
D9
A
NC
D10
VSS
A
Q10
VSS
VSS
Q11
VDDQ
VSS
D12
VDDQ
VDD
Q13
VDDQ
VDD
VDDQ
VDDQ
VDD
D14
VDDQ
VDD
Q14
VDDQ
VDD
D15
VDDQ
VSS
D16
VSS
VSS
Q16
VSS
A
Q17
A
A
A
A
A
Data input signals, sampled on the rising edge of K and K clocks during valid Write opera-
tions.
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active,
a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port
will cause D
to be ignored.
[17:0]
Byte Write Select 0, 1, active LOW. Sampled on the rising edge of the K and K clocks during
Write operations. Used to select which byte is written into the device during the current portion of
the Write operations. Bytes not written remain unaltered.
BWS
controls D
and BWS
0
[8:0]
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
Address Inputs. Sampled on the rising edge of the K (read address) and K (write address) clocks
for active Read and Write operations. These address inputs are multiplexed for both Read and
Write operations. Internally, the device is organized as 512K x 18 (2 arrays each of 256K x 18).
These inputs are ignored when the appropriate port is deselected.
Data Output signals. These pins drive out the requested data during a Read operation. Valid data
is driven out on the rising edge of both the C and C clocks during Read operations or K and K
when in single clock mode. When the Read port is deselected, Q
three-stated.
Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K). When
active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
three-stated following the next rising edge of the C clock. Each read access consists of a burst of
two sequential transfers.
CY7C1302DV25-167
167
500
6
7
8
K
NC
RPS
1
K
BWS
A
0
A
A
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VSS
VDD
VDDQ
VSS
VDD
VDDQ
VSS
VDD
VDDQ
VSS
VDD
VDDQ
VSS
VDD
VDDQ
VSS
VSS
VDDQ
VSS
VSS
VSS
A
A
VSS
C
A
A
C
A
A
Description
controls D
1
[17:9].
CY7C1302DV25
Unit
MHz
mA
9
10
11
NC/18M Gnd/72M
NC
NC
NC
Q8
NC
Q7
D8
NC
NC
D7
NC
D6
Q6
NC
NC
Q5
NC
NC
D5
VDDQ
VREF
ZQ
NC
Q4
D4
NC
D3
Q3
NC
NC
Q2
NC
Q1
D2
NC
NC
D1
NC
D0
Q0
A
TMS
TDI
are automatically
[17:0]
Page 2 of 18
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