Cypress Semiconductor CY7C1350G Ficha de especificações - Página 11

Procurar online ou descarregar pdf Ficha de especificações para Hardware informático Cypress Semiconductor CY7C1350G. Cypress Semiconductor CY7C1350G 16 páginas. Cypress 4-mbit (128k x 36) pipelined sram with nobl architecture specification sheet

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Switching Waveforms
NOP, STALL, and DESELECT Cycles
1
CLK
CEN
CE
ADV/LD
WE
BW
[A:D]
A1
ADDRESS
Data
In-Out (DQ)
WRITE
D(A1)
[23, 24]
ZZ Mode Timing
CLK
ZZ
I
SUPPLY
ALL INPUTS
(except ZZ)
Outputs (Q)
Notes:
22. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
23. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
24. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05524 Rev. *F
(continued)
[19, 20, 22]
2
3
4
A2
A3
D(A1)
READ
STALL
READ
Q(A2)
Q(A3)
DON'T CARE
t ZZ
t ZZI
I
DDZZ
5
6
7
A4
Q(A2)
Q(A3)
WRITE
STALL
NOP
D(A4)
UNDEFINED
t RZZI
DESELECT or READ Only
High-Z
DON'T CARE
CY7C1350G
8
9
10
A5
t
CHZ
D(A4)
Q(A5)
READ
DESELECT
CONTINUE
Q(A5)
DESELECT
t ZZREC
Page 11 of 15
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